A 6T-SRAM With a Post-Process Electron Injection Scheme That Pinpoints and Simultaneously Repairs Disturb Fails for 57% Less Read Delay and 31% Less Read Energy

A post-process carrier injection scheme for 6T-SRAM is proposed. The proposed scheme pinpoints and simultaneously repairs only cells that have low read disturb margin by injecting electrons to the strong pass gate transistor. Compared with the conventional electron injection scheme that injects electrons to either side of the pass gate transistor of all cells, the proposed scheme achieves 57% less BL delay, 31% less read energy, 32 ~ 256 times shorter injection time and 3% area reduction. The concept is validated with 2, 64, 128 kb SRAM in 40 nm standard CMOS process. Experiments show around 40 mV operation margin increase after the proposed injection.

[1]  Atsushi Kawasumi,et al.  A low supply voltage operation SRAM with HCI trimmed sense amplifiers , 2009, 2009 IEEE Asian Solid-State Circuits Conference.

[2]  Ching-Te Chuang,et al.  Relaxing Conflict Between Read Stability and Writability in 6T SRAM Cell Using Asymmetric Transistors , 2009, IEEE Electron Device Letters.

[3]  Ken Takeuchi,et al.  A 6T SRAM with a carrier-injection scheme to pinpoint and repair fails that achieves 57% faster read and 31% lower read energy , 2012, 2012 IEEE International Solid-State Circuits Conference.

[4]  Atsushi Kawasumi,et al.  Energy efficiency degradation caused by random variation in low-voltage SRAM and 26% energy reduction by Bitline Amplitude Limiting (BAL) scheme , 2011, IEEE Asian Solid-State Circuits Conference 2011.

[5]  Jin-Fu Li,et al.  Built-in redundancy analysis for memory yield improvement , 2003, IEEE Trans. Reliab..

[6]  H. Inokawa,et al.  Megabit-Class Size-Configurable 250-MHz SRAM Macrocells with a Squashed-Memory-Cell Architecture , 1999 .

[7]  Miyano Shinji,et al.  Self-Improvement of Cell Stability in SRAM by Post Fabrication Technique , 2012 .

[8]  H. Yamauchi,et al.  A 0.6 V Dual-Rail Compiler SRAM Design on 45 nm CMOS Technology With Adaptive SRAM Power for Lower VDD_min VLSIs , 2009, IEEE Journal of Solid-State Circuits.

[9]  H. Pilo,et al.  An SRAM Design in 65-nm Technology Node Featuring Read and Write-Assist Circuits to Expand Operating Voltage , 2007, IEEE Journal of Solid-State Circuits.

[10]  Zhenyu Qi,et al.  Improving SRAM Vmin and yield by using variation-aware BTI stress , 2010, IEEE Custom Integrated Circuits Conference 2010.

[11]  Kevin Zhang,et al.  A 32 nm High-k Metal Gate SRAM With Adaptive Dynamic Stability Enhancement for Low-Voltage Operation , 2011, IEEE Journal of Solid-State Circuits.

[12]  S. Miyano,et al.  Direct measurements, analysis, and post-fabrication improvement of noise margins in SRAM cells utilizing DMA SRAM TEG , 2010, 2010 Symposium on VLSI Technology.

[13]  Shuhei Tanakamaru,et al.  Analysis of Operation Margin and Read Speed in 6T- and 8T-SRAM with Local Electron Injected Asymmetric Pass Gate Transistor , 2012, IEICE Trans. Electron..

[14]  Natsuo Ajika,et al.  Device characteristics of 0.35 /spl mu/m P-channel DINOR flash memory using band-to-band tunneling-induced hot electron (BBHE) programming , 1999 .

[15]  Ken Takeuchi,et al.  Near Threshold Voltage Word-Line Voltage Injection Self-Convergence Scheme for Local Electron Injected Asymmetric Pass Gate Transistor 6T-SRAM , 2012, IEEE Transactions on Circuits and Systems I: Regular Papers.

[16]  Carl Radens,et al.  A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI Technology With 0.7 V Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements , 2011, IEEE Journal of Solid-State Circuits.

[17]  M. Yabuuchi,et al.  A 45nm 0.6V cross-point 8T SRAM with negative biased read/write assist , 2009, 2009 Symposium on VLSI Circuits.

[18]  Koji Nii,et al.  A 0.5V 100MHz PD-SOI SRAM with enhanced read stability and write margin by asymmetric MOSFET and forward body bias , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[19]  Shuhei Tanakamaru,et al.  Improvement of Read Margin and Its Distribution by $V_{\rm TH}$ Mismatch Self-Repair in 6T-SRAM With Asymmetric Pass Gate Transistor Formed by Post-Process Local Electron Injection , 2011, IEEE Journal of Solid-State Circuits.

[20]  Bongkoo Kang,et al.  Impact of Off-State Stress and Negative Bias Temperature Instability on Degradation of Nanoscale pMOSFET , 2012, IEEE Electron Device Letters.

[21]  T. Douseki,et al.  A 0.5-V 25-MHz 1-mW 256-kb MTCMOS/SOI SRAM for solar-power-operated portable personal digital equipment - sure write operation by using step-down negatively overdriven bitline scheme , 2006, IEEE Journal of Solid-State Circuits.

[22]  M. Suzuki,et al.  Post-Fabrication self-convergence scheme for suppressing variability in SRAM cells and logic transistors , 2006, 2009 Symposium on VLSI Technology.

[23]  N. Vallepalli,et al.  A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply , 2005, IEEE Journal of Solid-State Circuits.

[24]  Kevin Zhang,et al.  A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active VMIN-enhancing assist circuitry , 2012, 2012 IEEE International Solid-State Circuits Conference.

[25]  C. Radens,et al.  A Sub-600-mV, Fluctuation Tolerant 65-nm CMOS SRAM Array With Dynamic Cell Biasing , 2008, IEEE Journal of Solid-State Circuits.

[26]  K. Nii,et al.  90-nm process-variation adaptive embedded SRAM modules with power-line-floating write technique , 2006, IEEE Journal of Solid-State Circuits.

[27]  H. Morimura,et al.  1-V 100-MHz embedded SRAM techniques for battery-operated MTCMOS/SIMOX ASICs , 2000, IEEE Journal of Solid-State Circuits.

[28]  Atsushi Kawasumi,et al.  A process-variation-tolerant dual-power-supply SRAM with 0.179µm2 Cell in 40nm CMOS using level-programmable wordline driver , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.