On-chip oscilloscopes for noninvasive time-domain measurement of waveforms

High-speed digital design is becoming increasingly analog. In particular, interconnect response at high frequencies can be non-monotonic with "porch steps" and ringing. Crosstalk (both capacitive and inductive) can result in glitches on wires that can produce functional failures in receiving circuits. Most of these important effects are not addressed with traditional ATPG and BIST techniques, which are limited to the binary abstraction. In this work, we explore the feasibility of integrating primitive sampling oscilloscopes on-chip to provide waveforms on selective critical nets for test and diagnosis. The oscilloscopes rely on subsampling techniques to achieve sub-10 psec timing accuracy. High speed samplers are combined with DLLs and a simple 8-bit ADC to convert the waveforms into digital data that can be incorporated as part of the chip scan chain. We will describe the design and measurement of a chip we have fabricated to incorporate these oscilloscopes with a high frequency interconnect structure in a TSMC 0.25 /spl mu/m process.

[1]  M. Horowitz,et al.  Precise delay generation using coupled oscillators , 1993, 1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[2]  Gordon W. Roberts Improving the testability of mixed-signal integrated circuits , 1997, Proceedings of CICC 97 - Custom Integrated Circuits Conference.

[3]  Gordon W. Roberts,et al.  A high speed and area efficient on-chip analog waveform extractor , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[4]  Paul R. Gray,et al.  All-MOS analog-digital conversion techniques , 1978 .

[5]  Chih-Kong Ken Yang,et al.  A 0.8-/spl mu/m CMOS 2.5 Gb/s oversampling receiver and transmitter for serial links , 1996 .

[6]  C. Svensson,et al.  Measuring high-bandwidth signals in CMOS circuits , 1993 .

[7]  M. F. Tompsett,et al.  A 10-b 15-MHz CMOS recycling two-step A/D converter , 1990 .

[8]  Kenneth L. Shepard,et al.  Full-chip, three-dimensional, shapes-based RLC extraction , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[9]  Ron Ho,et al.  Applications of on-chip samplers for test and measurement of integrated circuits , 1998, 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215).

[10]  J.G. Maneatis,et al.  Low-jitter and process independent DLL and PLL based on self biased techniques , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[11]  Keith Lofstrom Early capture for boundary scan timing measurements , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[12]  A. Hajimiri,et al.  Jitter and phase noise in ring oscillators , 1999, IEEE J. Solid State Circuits.

[13]  J. Christiansen,et al.  An Integrated High Resolution CMOS Timing Generator Based on an Array of Delay Locked Loops , 1995, ESSCIRC '95: Twenty-first European Solid-State Circuits Conference.

[14]  D.A. Hodges,et al.  All-MOS charge-redistribution analog-to-digital conversion techniques. II , 1975, IEEE Journal of Solid-State Circuits.

[15]  C. Svensson,et al.  Time resolution of NMOS sampling switches used on low-swing signals , 1998 .

[16]  Krishnamurthy Soumyanath,et al.  Accurate on-chip interconnect evaluation: a time-domain technique , 1999 .