Towards Time-Predictable Data Caches for Chip-Multiprocessors

Future embedded systems are expected to use chip-multiprocessors to provide the execution power for increasingly demanding applications. Multiprocessors increase the pressure on the memory bandwidth and processor local caching is mandatory. However, data caches are known to be very hard to integrate into the worst-case execution time (WCET) analysis. We tackle this issue from the computer architecture side: provide a data cache organization that enables tight WCET analysis. Similar to the cache splitting between instruction and data, we argue to split the data cache for different data areas. In this paper we show cache simulation results for the split-cache organization, propose the modularization of the data cache analysis for the different data areas, and evaluate the implementation costs in a prototype chip-multiprocessor system.

[1]  Martin Schoeberl,et al.  A Time Predictable Instruction Cache for a Java Processor , 2004, OTM Workshops.

[2]  Benedikt Huber.  Worst-Case Execution Time Analysis for Real-Time Java , 2009 .

[3]  Reinhard Wilhelm,et al.  On Predicting Data Cache Behavior for Real-Time Systems , 1998, LCTES.

[4]  Martin Schoeberl.  Application Experiences with a Real-Time Java Processor , 2008 .

[5]  Martin Schoeberl,et al.  Time-predictable Cache Organization , 2009, 2009 Software Technologies for Future Dependable Distributed Systems.

[6]  David B. Whalley,et al.  Bounding worst-case instruction cache performance , 1994, 1994 Proceedings Real-Time Systems Symposium.

[7]  AbsInt Angewandte,et al.  Fast and Precise WCET Prediction by Separated Cache and Path Analyses , 1999 .

[8]  David B. Whalley,et al.  Timing Analysis for Data and Wrap-Around Fill Caches , 1999, Real-Time Systems.

[9]  Martin Schoeberl,et al.  A Java processor architecture for embedded real-time systems , 2008, J. Syst. Archit..

[10]  David A. Patterson,et al.  Reduced instruction set computers , 1985, CACM.

[11]  Jakob Engblom,et al.  Modeling complex flows for worst-case execution time analysis , 2000, Proceedings 21st IEEE Real-Time Systems Symposium.

[12]  Per Stenström,et al.  A method to improve the estimated worst-case performance of data caching , 1999, Proceedings Sixth International Conference on Real-Time Computing Systems and Applications. RTCSA'99 (Cat. No.PR00306).

[13]  Juan Ángel Pastor Franco,et al.  Real Time Teaching with Java: JPR3 , 2004 .

[14]  Cliff Click,et al.  Global code motion/global value numbering , 1995, PLDI '95.

[15]  Björn Lisper,et al.  Data caches in multitasking hard real-time systems , 2003, RTSS 2003. 24th IEEE Real-Time Systems Symposium, 2003.

[16]  Martin Schoeberl,et al.  Design and implementation of an efficient stack machine , 2005, 19th IEEE International Parallel and Distributed Processing Symposium.