论文信息 - A scalable and compact systolic architecture for linear solvers

A scalable and compact systolic architecture for linear solvers

We present a scalable design for accelerating the problem of solving a dense linear system of equations using LU Decomposition. A novel systolic array architecture that can be used as a building block in scientific applications is described and prototyped on a Xilinx Virtex 6 FPGA. This solver has a throughput of around 3.2 million linear systems per second for matrices of size N=4 and around 80 thousand linear systems per second for matrices of size N=16. In comparison with similar work, our design offers up to a 12-fold improvement in speed whilst requiring up to 50% less hardware resources. As a result, a linear system of size N=64 can be implemented on a single FPGA, whereas previous work was limited to a size of N=12 and resorted to complex multi-FPGA architectures to scale. Finally, the scalable design can be adapted to different sized problems with minimum effort.

Suhaib A. Fahmy | Keck Voon Ling | Kevin Shen-Hoong Ong

[1] Chunru Wan. Systolic algorithms and applications , 1996 .

[2] Suhaib A. Fahmy,et al. Iterative floating point computation using FPGA DSP blocks , 2013, 2013 23rd International Conference on Field programmable Logic and Applications.

[3] Douglas L. Maskell,et al. A lean FPGA soft processor built using a DSP block , 2012, FPGA '12.

[4] Eric C. Kerrigan,et al. Model predictive control for deeply pipelined field-programmable gate array implementation: algorithms and circuitry , 2012 .

[5] Ali Irturk,et al. GUSTO : general architecture design utility and synthesis tool for optimization , 2009 .

[6] James Reinders. Systolic Arrays , 2011, Encyclopedia of Parallel Computing.

[7] Brett Ninness,et al. Implementation of linear model predictive control using a field-programmable gate array , 2012 .

[8] Joseph R. Cavallaro,et al. FPGA Implementation of Matrix Inversion Using QRD-RLS Algorithm , 2005, Conference Record of the Thirty-Ninth Asilomar Conference onSignals, Systems and Computers, 2005..

[9] George A. Constantinides,et al. Optimizing memory bandwidth use and performance for matrix-vector multiplication in iterative methods , 2011, TRETS.