Parameter Variation at Near Threshold Voltage : The Power Efficiency versus Resilience Tradeoff

[1]  Xiang Pan,et al.  VRSync: Characterizing and eliminating synchronization-induced voltage emergencies in many-core processors , 2012, 2012 39th Annual International Symposium on Computer Architecture (ISCA).

[2]  Nam Sung Kim,et al.  Cost-effective power delivery to support per-core voltage domains for power-constrained processors , 2012, DAC Design Automation Conference 2012.

[3]  Xiang Pan,et al.  Booster: Reactive core acceleration for mitigating the effects of process variation and application imbalance in low-voltage chips , 2012, IEEE International Symposium on High-Performance Comp Architecture.

[4]  Bishop Brock,et al.  Active management of timing guardband to save energy in POWER7 , 2011, 2011 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[5]  L. Chang,et al.  Improving the energy/power constraint for technology optimization , 2011, 2011 International Electron Devices Meeting.

[6]  Nam Sung Kim,et al.  Low-voltage on-chip cache architecture using heterogeneous cell sizes for high-performance processors , 2011, 2011 IEEE 17th International Symposium on High Performance Computer Architecture.

[7]  James Dinan,et al.  Parichute: Generalized Turbocode-Based Error Correction for Near-Threshold Caches , 2010, 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture.

[8]  Yu Cao,et al.  Workload-adaptive process tuning strategy for power-efficient multi-core processors , 2010, 2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED).

[9]  Wei Wu,et al.  Reducing cache power with low-cost, multi-bit error-correcting codes , 2010, ISCA.

[10]  David Blaauw,et al.  Near-Threshold Computing: Reclaiming Moore's Law Through Energy Efficient Integrated Circuits , 2010, Proceedings of the IEEE.

[11]  Robert H. Dennard,et al.  Practical Strategies for Power-Efficient Computing Technologies , 2010, Proceedings of the IEEE.

[12]  Jan M. Rabaey,et al.  Ultralow-Power Design in Near-Threshold Region , 2010, Proceedings of the IEEE.

[13]  Wei Wu,et al.  Improving cache lifetime reliability at ultra-low voltages , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[14]  Nam Sung Kim,et al.  Frequency and yield optimization using power gates in power-constrained designs , 2009, ISLPED.

[15]  Nam Sung Kim,et al.  Optimizing total power of many-core processors considering voltage scaling limit and process variations , 2009, ISLPED.

[16]  David Bol,et al.  Technology flavor selection and adaptive techniques for timing-constrained 45nm subthreshold circuits , 2009, ISLPED.

[17]  M. Erez,et al.  Memory mapped ECC: low-cost error protection for last level caches , 2009, ISCA '09.

[18]  Meeta Sharma Gupta,et al.  An event-guided approach to reducing voltage noise in processors , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[19]  Meeta Sharma Gupta,et al.  Voltage emergency prediction: Using signatures to reduce operating margins , 2009, 2009 IEEE 15th International Symposium on High Performance Computer Architecture.

[20]  David Blaauw,et al.  Reconfigurable energy efficient near threshold cache architectures , 2008, 2008 41st IEEE/ACM International Symposium on Microarchitecture.

[21]  Josep Torrellas,et al.  Facelift: Hiding and slowing down aging in multicores , 2008, 2008 41st IEEE/ACM International Symposium on Microarchitecture.

[22]  Meeta Sharma Gupta,et al.  System level analysis of fast, per-core DVFS using on-chip switching regulators , 2008, 2008 IEEE 14th International Symposium on High Performance Computer Architecture.

[23]  Meeta Sharma Gupta,et al.  DeCoR: A Delayed Commit and Rollback mechanism for handling inductive noise in processors , 2008, 2008 IEEE 14th International Symposium on High Performance Computer Architecture.

[24]  Nanning Zheng,et al.  Realization of L2 Cache Defect Tolerance Using Multi-bit ECC , 2008, 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems.

[25]  Diana Marculescu,et al.  Characterizing chip-multiprocessor variability-tolerance , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[26]  Josep Torrellas,et al.  Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors , 2008, 2008 International Symposium on Computer Architecture.

[27]  Gu-Yeon Wei,et al.  ReVIVaL: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency , 2008, 2008 International Symposium on Computer Architecture.

[28]  J. Torrellas,et al.  VARIUS: A Model of Process Variation and Resulting Timing Errors for Microarchitects , 2008, IEEE Transactions on Semiconductor Manufacturing.

[29]  Babak Falsafi,et al.  Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding , 2007, 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007).

[30]  Josep Torrellas,et al.  Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing , 2007, 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007).

[31]  David Blaauw,et al.  Energy efficient near-threshold chip multi-processing , 2007, Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07).

[32]  William V. Huott,et al.  Comparison of Split-Versus Connected-Core Supplies in the POWER6 Microprocessor , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[33]  K. Skadron,et al.  Impact of Process Variations on Multicore Performance Symmetry , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[34]  Meeta Sharma Gupta,et al.  Understanding Voltage Variations in Chip Multiprocessors using a Distributed Power-Delivery Network , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[35]  Yejun He,et al.  Performance Evaluation of Adaptive Two-Dimensional Turbo Product Codes Composed of Hamming Codes , 2007, 2007 IEEE International Conference on Integration Technology.

[36]  David M. Brooks,et al.  Mitigating the Impact of Process Variations on Processor Register Files and Execution Units , 2006, 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06).

[37]  Emil Talpes,et al.  Variability and energy awareness: a microarchitecture-level perspective , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[38]  Dennis Sylvester,et al.  A new algorithm for improved VDD assignment in low power dual VDD systems , 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).

[39]  Sivakumar Velusamy,et al.  Temperature-aware microarchitecture , 2003, 30th Annual International Symposium on Computer Architecture, 2003. Proceedings..

[40]  Rajendran Panda,et al.  Statistical timing analysis using bounds and selective enumeration , 2002, TAU '02.

[41]  Nhon Quach,et al.  High Availability and Reliability in the Itanium Processor , 2000, IEEE Micro.

[42]  Christian Bienia,et al.  Benchmarking modern multiprocessors , 2011 .

[43]  Sule Ozev,et al.  Quantifying the Impact of Process Variability on Microprocessor Behavior , 2006 .

[44]  A.P. Chandrakasan,et al.  Ultra-dynamic Voltage scaling (UDVS) using sub-threshold operation and local Voltage dithering , 2006, IEEE Journal of Solid-State Circuits.