Transient power in CMOS gates driving LC transmission lines

The dynamic and short-circuit power consumption of a CMOS gate driving an LC transmission line as a limiting case of an RLC transmission line is investigated in this paper. Closed form solutions for the output voltage and short-circuit power of a CMOS gate driving an LC transmission line are presented. These solutions agree with circuit simulations within 11% error for a wide range of transistor widths and line impedances for a 0.25 /spl mu/m CMOS technology. The ratio of the short-circuit to dynamic power is shown to be less than 7% for CMOS gates driving LC transmission lines where the line is matched or underdriven. The total power consumption is expected to decrease as inductance effects becomes more significant as compared to an RC dominated interconnect line.

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