Selective triple Modular redundancy (STMR) based single-event upset (SEU) tolerant synthesis for FPGAs

We present a design technique for hardening combinational circuits mapped onto Xilinx Virtex FPGAs against single-event upsets (SEUs). The signal probabilities of the lines can be used to detect SEU sensitive subcircuits of a given combinational circuit. The circuit can be hardened against SEUs by selectively applying triple modular redundancy (STMR) to these sensitive subcircuits. However, there is an increase in the number of the voter circuits required for the STMR circuits. Virtex has abundant number of tri-state buffers that can be employed to construct SEU immune majority voter circuits. We also present a SEU fault insertion simulator designed to introduce errors representing SEUs in the circuits. STMR method is thoroughly tested on MCNC'91 benchmarks. With a small loss of SEU immunity, the proposed STMR method can greatly reduce the area overhead of the hardened circuit when compared to the state-of-the-art triple modular redundancy (TMR). STMR method along with the readback and reconfiguration feature of Virtex can result in very high SEU immunity.

[1]  Gary S. Ditlow,et al.  Random Pattern Testability , 1984, IEEE Transactions on Computers.

[2]  J. Canaris,et al.  SEU hardened memory cells for a CCSDS Reed-Solomon encoder , 1991 .

[3]  Joseph G. Tront,et al.  Probability of latching single event upset errors in VLSI circuits , 1991, IEEE Proceedings of the SOUTHEASTCON '91.

[4]  S. Whitaker,et al.  Low power SEU immune CMOS memory circuits , 1992 .

[5]  P. R. Stephan,et al.  SIS : A System for Sequential Circuit Synthesis , 1992 .

[6]  Jr. Leonard R. Rockett.  Simulated SEU hardened scaled CMOS SRAM cell design using gated resistors , 1992 .

[7]  J. Canaris,et al.  Design And Testing Of SEU/ SEL Immune Memory And Logic Circuits In A Commercial Cmos Process , 1993, 1993 IEEE Radiation Effects Data Workshop.

[8]  Michael Nicolaidis,et al.  SEU-tolerant SRAM design based on current monitoring , 1994, Proceedings of IEEE 24th International Symposium on Fault- Tolerant Computing.

[9]  Raoul Velazco,et al.  Two CMOS memory cells suitable for the design of SEU-tolerant VLSI circuits , 1994 .

[10]  J. Canaris,et al.  Circuit techniques for the radiation environment of space , 1995, Proceedings of the IEEE 1995 Custom Integrated Circuits Conference.

[11]  T. Calin,et al.  A low-cost, highly reliable SEU-tolerant SRAM: prototype and test results , 1995 .

[12]  S. Katkoori,et al.  Profile-driven behavioral synthesis for low-power VLSI systems , 1995, IEEE Design & Test of Computers.

[13]  Radu Marculescu,et al.  Improving the efficiency of power simulators by input vector compaction , 1996, DAC '96.

[14]  T. Calin,et al.  Upset hardened memory design for submicron CMOS technology , 1996 .

[15]  Kenneth A. LaBel,et al.  Single-event-effect mitigation from a system perspective , 1996 .

[16]  Joel Hass.  Probabilistic Estimates of Upset Caused by Single Event Transients , 1999 .

[17]  M. Caffrey,et al.  SEU Mitigation Techniques for Virtex FPGAs in Space Applications , 1999 .

[18]  P. H. Eaton,et al.  SEU and SET Mitigation Techniques for FPGA Circuit and Configuration Bit Storage Design , 2005 .