Clock monitoring circuit

The circuit comprises a monitoring clock receiver(1), a counter reset generator(4) for generating a first reset signal in response to the received monitoring clock, a reset signal receiver(2) for receiving a second reset signal and synchronizing the received second reset signal with the monitoring clock or a reference clock, a monitoring counter circuit(5) sampling and counting the reference clock in response to the first and second reset signals to monitor the clock, a NAND logic means(7) outputting the monitored result in response to an output signal from the monitoring counter if a clock error is determined according to the monitored result, and an output hold circuit(16) holding the monitored result from the NAND logic device when the monitoring clock is abnormal.