Fast extended test access via JTAG and FPGAs

This paper describes a new test access protocol for system-level testing of printed circuit boards for manufacturing defects. We show that the protocol can be based on standard Boundary Scan (BS) instructions and test access mechanism (TAM). It means that the methodology does not require any changes/redesign of hardware and can be immediately implemented in the electronic manufacturing. Our solution needs however a proper software support and availability of programmable devices (FPGAs, CPLDs, etc.) on the board under test. The new technique dramatically extends the applicability of BS testing in the reality of modern complex on-board data transfer buses and protocols. Potentially, it can also increase the speed of in-system programming of flash memories and other tasks that are traditionally performed using BS.

[1]  Benoit Nadeau-Dostie,et al.  An embedded technique for at-speed interconnect testing , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[2]  David A. Bonnett.  Design for In-System Programming , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[3]  Kenneth P. Parker,et al.  The Boundary-Scan Handbook , 1992, Springer US.

[4]  Mike Ricchetti,et al.  IEEE 1149.6 - a practical perspective , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[5]  Artur Jutman,et al.  At-speed on-chip diagnosis of board-level interconnect faults , 2004, Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004..

[6]  Bill Eklow,et al.  IEEE 1149.6 - a practical perspective , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[7]  Heiko Ehrenberg.  IEEE P1581 - Getting More Board Test Out of Boundary Scan , 2006, 2006 IEEE International Test Conference.