The positive trigger voltage lowering effect for latch-up

In this paper, a new latch-up phenomenon, in which the positive trigger voltage V/sub trg+/ is smaller than the theoretical value, based on the two-step activation diode model, is found and analyzed by TCAD simulation. Based on the simulation result, an analytical model for the positive trigger point is developed and methodologies for evaluating the positive trigger point, varying with the geometry layout of the latch-up test patterns, are proposed. The calculated positive trigger current and trigger voltage fit the measurement results very well, so that the proposed method is efficient for evaluating the positive triggering point.

[1]  H.P. Zappe,et al.  A transient analysis of latchup in bulk CMOS , 1983, IEEE Transactions on Electron Devices.

[2]  Solid-State Electronics , 1955, Nature.