A testable design for electrical interconnect tests of 3D ICs

A testable design method for electrical testing is proposed in this paper to detect open defects occurring at interconnects between dies in a 3D IC and locate the defective interconnects. An IEEE 1149.1 test circuit is utilized to provide a test input vector to a targeted interconnect in the electrical tests. Feasibility of the electrical tests is evaluated by Spice simulation. It is shown by the experiments that a hard open defect and a resistive open defect can be detected at a test speed of 1GHz.

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