A 45nm SOI CMOS Class-D mm-Wave PA with >10Vpp differential swing

The ever-increasing demand for low-cost portable communication devices pushes for higher integration of wireless transceivers in deeply-scaled silicon technologies. Given the overwhelming digital content of a mobile platform, ideally, the RF components should be realized with topologies that allow for their seamless scaling into 22nm and 14nm CMOS technologies. The Power Amplifier (PA) remains one of the most challenging circuit blocks to implement in nanoscale CMOS due to the strict requirements for output power, efficiency and linearity imposed by wireless communication standards. The low breakdown voltage of nanoscale MOSFETs limits the maximum drain voltage swing and the maximum achievable output power. In order to circumvent this problem, a typical approach is to increase the device size and use a reactive matching network to transform the load resistance to a value significantly lower than 50Ω. Nevertheless, due to the typically low-Q passive components that can be manufactured in a nanoscale CMOS process, and because of the high impedance transformation ratio involved, most of the additional output power that would be gained by increasing the device size is wasted in resistive losses in the matching networks, resulting in poor efficiency. This problem is exacerbated at mm-Wave frequencies where the loss of the passive components is even higher, and using lower fT/fMAX thicker oxide or extended drain MOS devices [1] is not viable.