A Self-Consistent Substrate Thermal Profile Estimation Technique for Nanoscale ICs—Part I: Electrothermal Couplings and Full-Chip Package Thermal Model

As CMOS technology scales to nanometer regime, power dissipation issues and associated thermal problems have emerged as critical design concerns in most high-performance integrated circuits (ICs) including microprocessors. In this scenario, accurate estimation of the silicon junction (substrate or die) temperature is crucial for various performance analyses and chip-level thermal management. This paper introduces the notion of self-consistency in the junction temperature estimation by taking into account various electrothermal couplings between chip power, average junction temperature, operating frequency, and supply voltage. The self-consistent solutions of the average junction temperature are shown to have significant implications for various chip-level power, performance, reliability, and cooling cost tradeoffs. Moreover, a realistic package thermal model is introduced that comprehends different packaging layers and noncubic structure of the package, which are not accounted for in traditional analyses. The model is subsequently incorporated in the self-consistent substrate thermal profile estimation, which is discussed in Part II with implications for power estimation and thermal management in nanometer-scale CMOS technologies.

[1]  R. D. Cess.  The effect of radiation upon forced-convection heat transfer , 1961 .

[2]  R. Viswanath.  Thermal Performance Challenges from Silicon to Systems , 2000 .

[3]  Kaustav Banerjee,et al.  Full chip thermal analysis of planar (2-D) and vertically integrated (3-D) high performance ICs , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

[4]  Kaustav Banerjee,et al.  Simultaneous optimization of supply and threshold voltages for low-power and high-performance circuits in the leakage dominant era , 2004, Proceedings. 41st Design Automation Conference, 2004..

[5]  M. K. Iyer,et al.  Addressing packaging challenges , 2002 .

[6]  Peter M. Zeitzoff,et al.  MOSFET scaling trends and challenges through the end of the roadmap , 2004, Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571).

[7]  Anantha Chandrakasan,et al.  Full-chip sub-threshold leakage power prediction model for sub-0.18 μm CMOS , 2002, ISLPED '02.

[8]  Anantha Chandrakasan,et al.  Full-chip subthreshold leakage power prediction model for sub-0 . 18 m CMOS , 2002 .

[9]  K. Banerjee,et al.  Impact of off-state leakage current on electromigration design rules for nanometer scale CMOS technologies , 2004, 2004 IEEE International Reliability Physics Symposium. Proceedings.

[10]  Sheng-Chih Lin,et al.  A self-consistent junction temperature estimation methodology for nanometer scale ICs with implications for performance and thermal management , 2003, IEEE International Electron Devices Meeting 2003.

[11]  Shekhar Y. Borkar,et al.  Design challenges of technology scaling , 1999, IEEE Micro.

[12]  Kaustav Banerjee,et al.  Electrothermal engineering in the nanometer era: from devices and interconnects to circuits and systems , 2006, Asia and South Pacific Conference on Design Automation, 2006..

[13]  K. Banerjee,et al.  Global (interconnect) warming , 2001 .

[14]  Rane Milind Viswanath,et al.  Thermal Performance Challenges from Silicon to Systems 1 Thermal Performance Challenges from Silicon to Systems , 2000 .

[15]  A. Amerasekera,et al.  The effect of interconnect scaling and low-k dielectric on the thermal characteristics of the IC metal , 1996, International Electron Devices Meeting. Technical Digest.

[16]  Sheng-Chih Lin,et al.  A Self-Consistent Substrate Thermal Profile Estimation Technique for Nanoscale ICs—Part II: Implementation and Implications for Power Estimation and Thermal Management , 2007, IEEE Transactions on Electron Devices.

[17]  G.E. Moore,et al.  Cramming More Components Onto Integrated Circuits , 1998, Proceedings of the IEEE.

[18]  R.H. Dennard,et al.  Design Of Ion-implanted MOSFET's with Very Small Physical Dimensions , 1974, Proceedings of the IEEE.

[19]  Kaustav Banerjee,et al.  A power-optimal repeater insertion methodology for global interconnects in nanometer designs , 2002 .

[20]  Kaustav Banerjee,et al.  A thermally-aware methodology for design-specific optimization of supply and threshold voltages in nanometer scale ICs , 2005, 2005 International Conference on Computer Design.

[21]  K. Banerjee,et al.  Scaling analysis of multilevel interconnect temperatures for high-performance ICs , 2005, IEEE Transactions on Electron Devices.

[22]  Vivek De,et al.  Technology and design challenges for low power and high performance [microprocessors] , 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477).

[23]  P.P. Gelsinger,et al.  Microprocessors for the new millennium: Challenges, opportunities, and new frontiers , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[24]  M. N. Özişik.  Boundary value problems of heat conduction , 1989 .

[25]  James Tschanz,et al.  Parameter variations and impact on circuits and microarchitecture , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[26]  Gordon E. Moore,et al.  Progress in digital integrated electronics , 1975 .

[27]  J. Liaw,et al.  Leakage scaling in deep submicron CMOS for SoC , 2002 .

[28]  Ravi Prasher,et al.  Nano and Micro Technology-Based Next-Generation Package-Level Cooling Solutions , 2005 .

[29]  Amitava Chatterjee,et al.  An investigation of the impact of technology scaling on power wasted as short-circuit current in low voltage static CMOS circuits , 1996, ISLPED.