Low power GDI ALU design with mixed logic adder functionality

In this paper, we present a low power Arithmetic Logic Unit (ALU) in 90nm technology using optimized Gate Diffusion Input (GDI) design style. Inspired by the basic ten transistor adder cell compactness, we redesign the architecture of the ALU, by combining the adder and logic functionality in a modified ten transistor cell. The design is compact compared to other designs. For low power applications, we add a transmission gate to isolate the front-end logic section from the backend adder section of the same cell. This restricts power activity only to the logic section when the ALU performs logic operations, leading to more than 2X power savings compared to no-transmission gate implementation. All this comes with less than 9% increase in delay at 1.5V for an 8-bit ALU implementation, and around 50% reduction in the transistor count compared to a traditional GDI ALU implementation with separate logic and arithmetic functionality and enable signals. The design is simulated and verified using a 90nm TSMC design kit.