A 6-bit Fully Binary Digital-to-Analog Converter in 0.25-$\mu{\hbox {m}}$ SiGe BiCMOS for Optical Communications

This paper presents an approach to implement a high-speed binary weighted digital-to-analog converter (DAC). A different current switching mechanism is proposed that improves the dynamic performance of binary weighted DACs. Circuit simulation shows an improvement of the rise (fall) time mismatch by a factor of 2 over the conventional structure. It is shown that in a conventional high-speed binary DAC implemented with differential pairs, the spurious-free dynamic range (SFDR) can be degraded by nearly 6 dB due to the different rise (fall) times of the current switches. Using the proposed current switches, a fully binary weighted DAC with nominal resolution of 6 bit has been fabricated in 0.25-μm SiGe technology. The measured SFDR is higher than 30.1 dBc up to 5.9-GHz input signal with a 13.4-GHz clock. The DAC can provide 1.1-V peak-to-peak differential output swing over 50 Ω while dissipating 1050 mW. Full-scale 20%-80% fall time and 2% settling time are measured below 18 and 45 ps, respectively.

[1]  Xueyang Geng,et al.  A 9-bit 2.9 GHz direct digital synthesizer MMIC with direct digital frequency and phase modulations , 2009, 2009 IEEE MTT-S International Microwave Symposium Digest.

[2]  Yiannos Manoli,et al.  ΣΔ Data Converters , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[3]  Behzad Razavi,et al.  Principles of Data Conversion System Design , 1994 .

[4]  Bertrand Meyer.  Wide-Bandwidth High Dynamic Range D/A Converters , 1995 .

[5]  Michiel Steyaert,et al.  A 10–Bit 1.6-GS/s 27-mW Current-Steering D/A Converter With 550-MHz 54-dB SFDR Bandwidth in 130-nm CMOS , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

[6]  D. Baranauskas,et al.  A 0.36W 6b up to 20GS/s DAC for UWB Wave Formation , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[7]  J. Jacob Wikner,et al.  CMOS Data Converters for Communications , 2000 .

[8]  Rudy Van De Plassche.  Integrated analog-to-digital and digital-to-analog converters / Rudy Van De Plassche , 1994 .

[9]  T. Duthel,et al.  Coherent Equalization and POLMUX-RZ-DQPSK for Robust 100-GE Transmission , 2008, Journal of Lightwave Technology.

[10]  J.W. Haslett,et al.  Analysis and design of HBT Cherry-Hooper amplifiers with emitter-follower feedback for optical communications , 2004, IEEE Journal of Solid-State Circuits.

[11]  M. Moller,et al.  Challenges in the Cell-Based Design of Very-High-Speed SiGe-Bipolar ICs at 100 Gb/s , 2008, IEEE Journal of Solid-State Circuits.

[12]  Bang-Sup Song,et al.  A 14b , 100-MS / s CMOS DAC Designed for Spectral Performance , 1999 .

[13]  P. Schvan,et al.  A 22GS/s 6b DAC with integrated digital ramp generator , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[14]  Tao Chen,et al.  The Analysis and Improvement of a Current-Steering DAC's Dynamic SFDR—II: The Output-Dependent Delay Differences , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

[15]  Georges Gielen,et al.  Behavioral model of reusable D/A converters , 1999 .

[16]  P. N. Paraskevopoulos,et al.  Modern Control Engineering , 2001 .

[17]  S. Kametani,et al.  16-QAM modulation by polar coordinate transformation with a single dual drive Mach-Zehnder Modulator , 2009, 2009 Conference on Optical Fiber Communication - incudes post deadline papers.

[18]  Chi-Hung Lin,et al.  A 12 bit 2.9 GS/s DAC With IM3 $ ≪ -$60 dBc Beyond 1 GHz in 65 nm CMOS , 2009, IEEE Journal of Solid-State Circuits.

[19]  Hans-Martin Rein,et al.  Design considerations for very-high-speed Si-bipolar IC's operating up to 50 Gb/s , 1996, IEEE J. Solid State Circuits.

[20]  Robert G. Meyer,et al.  Analysis and Design of Analog Integrated Circuits , 1993 .

[21]  Tao Chen,et al.  The analysis and improvement of a current-steering DACs dynamic SFDR-I: the cell-dependent delay differences , 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

[22]  K. Ola Andersson,et al.  Modeling of glitches due to rise/fall asymmetry in current-steering digital-to-analog converters , 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.

[23]  A. Amirkhany,et al.  A 12-GS/s Phase-Calibrated CMOS Digital-to-Analog Converter for Backplane Communications , 2008, IEEE Journal of Solid-State Circuits.

[24]  Bang-Sup Song,et al.  A 14 b 100 Msample/s CMOS DAC designed for spectral performance , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

[25]  Mahdi Khafaji,et al.  A 6 bit linear binary RF DAC in 0.25µm SiGe BiCMOS for communication systems , 2010, 2010 IEEE MTT-S International Microwave Symposium.

[26]  Eduard Alarcón,et al.  Mismatch and dynamic modeling of current sources in current-steering CMOS D/A converters: an extended design procedure , 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.

[27]  Katsuhiko Ogata,et al.  Modern control engineering (3rd ed.) , 1996 .

[28]  D. Knoll,et al.  High-performance BiCMOS technologies without epitaxially-buried subcollectors and deep trenches , 2006, 2006 International SiGe Technology and Device Meeting.