On the Interaction Between Power-Aware FPGA CAD Algorithms

As Field-Programmable Gate Array (FPGA) power consumptioncontinues to increase, lower power FPGA circuitry, architectures,and Computer-Aided Design (CAD) tools need to be developed.Before designing low-power FPGA circuitry, architectures, orCAD tools, we must first determine where the biggest savings (interms of energy dissipation) are to be made and whether thesesavings are cumulative. In this paper, we focus on FPGA CADtools. Specifically, we describe a new power-aware CAD flow forFPGAs that was developed to answer the above questions.Estimating energy using very detailed post-route power and delaymodels, we determine the energy savings obtained by our power-awaretechnology mapping, clustering, placement, and routingalgorithms and investigate how the savings behave when thealgorithms are applied concurrently. The individual savings of thepower-aware technology-mapping, clustering, placement, androuting algorithms were 7.6%, 12.6%, 3.0%, and 2.6%respectively. The majority of the overall savings were achievedduring the technology mapping and clustering stages of the power-awareFPGA CAD flow. In addition, the savings were mostlycumulative when the individual power-aware CAD algorithmswere applied concurrently with an overall energy reduction of 22.6%.

[1]  Jason Cong,et al.  DAG-Map: graph-based FPGA technology mapping for delay optimization , 1992, IEEE Design & Test of Computers.

[2]  Jason Helge Anderson,et al.  Power-aware technology mapping for LUT-based FPGAs , 2002, 2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings..

[3]  Jason Cong,et al.  Cut ranking and pruning: enabling a general and efficient FPGA mapping solution , 1999, FPGA '99.

[4]  Malgorzata Marek-Sadowska,et al.  Efficient circuit clustering for area and power reduction in FPGAs , 2002, TODE.

[5]  Jason Cong,et al.  Simultaneous Depth and Area Minimization in LUT-based FPGA Mapping , 1995, Third International ACM Symposium on Field-Programmable Gate Arrays.

[6]  P. R. Stephan,et al.  SIS : A System for Sequential Circuit Synthesis , 1992 .

[7]  Srinivas Katkoori,et al.  LUT-based FPGA technology mapping for power minimization with optimal depth , 2001, Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems.

[8]  Carl Ebeling,et al.  PathFinder: A Negotiation-Based Performance-Driven Router for FPGAs , 1995, Third International ACM Symposium on Field-Programmable Gate Arrays.

[9]  Jason Cong,et al.  FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  Vaughn Betz,et al.  Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density , 1999, FPGA '99.

[11]  Vaughn Betz,et al.  Timing-driven placement for FPGAs , 2000, FPGA '00.

[12]  Vaughn Betz.  Architecture and CAD for speed and area optimization of FPGAs , 1998 .

[13]  SinghAmit,et al.  Efficient circuit clustering for area and power reduction in FPGAs , 2002 .

[14]  Farid N. Najm.  Low-pass filter for computing the transition density in digital circuits , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[15]  Steven J. E. Wilton,et al.  A Flexible Power Model for FPGAs , 2002, FPL.