3D integration using inductive coupling and coupled resonator (Invited)
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[1] Tadahiro Kuroda,et al. 3D clock distribution using vertically/horizontally-coupled resonators , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.
[2] Tadahiro Kuroda,et al. A 352Gb/s inductive-coupling DRAM/SoC interface using overlapping coils with phase division multiplexing and ultra-thin fan-out wafer level package , 2014, 2014 Symposium on VLSI Circuits Digest of Technical Papers.
[3] Eby G. Friedman,et al. Clock distribution networks for 3-D ictegrated Circuits , 2008, 2008 IEEE Custom Integrated Circuits Conference.
[4] T. Kuroda,et al. Perspective of Low-Power and High-Speed Wireless Inter-Chip Communications for SiP Integration , 2006, 2006 European Solid-State Device Research Conference.
[5] Tadahiro Kuroda,et al. A 2.5Gb/s/ch 4PAM inductive-coupling transceiver for non-contact memory card , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).
[6] N. Miura,et al. A 1.2Gb/s/pin wireless superconnect based on inductive inter-chip signaling (IIS) , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).
[7] Tadahiro Kuroda,et al. An 8Tb/s 1pJ/b 0.8mm2/Tb/s QDR inductive-coupling interface between 65nm CMOS GPU and 0.1µm DRAM , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).
[8] Yasuhiro Morita,et al. Wireless DC voltage transmission using inductive-coupling channelfor highly-parallel wafer-level testing , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.