Investigation into voltage and process variation-aware manufacturing test

Traditional test methods that use abstract fault models potentially results in low defect coverage and test escapes for ICs with multiple supply voltage (Vdd) settings for adaptive power management, and in the presence of process variation. In this paper, we address two important defect types, resistive bridge defects and full open defects, and present foundational work on variation-aware test methods. To test ICs with multiple Vdds, Multi-Vdd Test Generation (MVTG) produces Vdd-specific test sets, such that tests are applied using the most effective Vdd. For Process Variation-aware Test Generation (PVTG), we target the most significant test escapes, guided by a novel process variation-aware metric for test quality, called test robustness. We implemented our test methods, and integrated them into a flow of commercial EDA tools. Experimental results on benchmark designs and realistic defects, extracted from layout, show that our test methods achieve high defect coverage while keeping the test sets size low. This serves as proof-of-concept for variation-aware test.

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