Fan-Out Wafer/Panel-Level Packaging for Heterogeneous Integrations

The first fan-out wafer-level packaging (FOWLP) U.S. patent was filed by Infineon on October 31, 2001.

[1]  B. Banijamali,et al.  Outstanding and innovative reliability study of 3D TSV interposer and fine pitch solder micro-bumps , 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

[2]  John H Lau,et al.  Fan-out wafer-level packaging for 3D IC heterogeneous integration , 2018, 2018 China Semiconductor Technology International Conference (CSTIC).

[3]  Fengman Liu,et al.  Experimental Verification and Optimization Analysis of Warpage for Panel-Level Fan-Out Package , 2017, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[5]  Naoki Hayashi,et al.  A novel Wafer level Fan-out Package (WFOP™) applicable to 50um pad pitch interconnects , 2011, 2011 IEEE 13th Electronics Packaging Technology Conference.

[6]  Andre Cardoso,et al.  Thermally enhanced FOWLP-development of a Power-eWLB demonstrator , 2015, 2015 IEEE 65th Electronic Components and Technology Conference (ECTC).

[7]  Kilsoo Kim,et al.  Advanced Fan-Out Package SI/PI/Thermal Performance Analysis of Novel RDL Packages , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).

[8]  Clark Hu,et al.  Wafer-Level Integration of an Advanced Logic-Memory System Through the Second-Generation CoWoS Technology , 2017, IEEE Transactions on Electron Devices.

[9]  M. Kawano,et al.  Three-Dimensional Packaging Technology for Stacked DRAM With 3-Gb/s Data Transfer , 2008, IEEE Transactions on Electron Devices.

[10]  WonChul Do,et al.  SLIM (TM), High Density Wafer Level Fan-Out Package Development with Submicron RDL , 2017, 2017 IEEE 67th Electronic Components and Technology Conference (ECTC).

[11]  Kai Liu,et al.  High-speed packages with imperfect power and ground planes , 2013, 2013 IEEE 63rd Electronic Components and Technology Conference.

[12]  A. Kumar,et al.  Design and development of a multi-die embedded micro wafer level package , 2008, 2008 58th Electronic Components and Technology Conference.

[13]  K. Soejima,et al.  A 3D Packaging Technology for 4 Gbit Stacked DRAM with 3 Gbps Data Transfer , 2006, 2006 International Electron Devices Meeting.

[15]  S.B. Park,et al.  Design Guideline of 2.5D Package with Emphasis on Warpage Control and Thermal Management , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).

[16]  J. Lau,et al.  Chip-First Fan-Out Panel-Level Packaging for Heterogeneous Integration , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).

[17]  John H. Lau,et al.  Redistribution Layers (RDLs) for 2.5D/3D IC Integration , 2013 .

[18]  Chin-Li Kao,et al.  Wafer Warpage Experiments and Simulation for Fan-Out Chip on Substrate , 2016, 2016 IEEE 66th Electronic Components and Technology Conference (ECTC).

[19]  Tzu-Chun Tang,et al.  InFO_AiP Technology for High Performance and Compact 5G Millimeter Wave System Integration , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).

[20]  John H. Lau,et al.  Recent Advances and New Trends in Flip Chip Technology , 2016 .

[21]  J. Lau,et al.  Development of chip-first and die-up fan-out wafer level packaging , 2017, 2017 IEEE 19th Electronics Packaging Technology Conference (EPTC).

[22]  Wei-Yuan Cheng,et al.  Evaluation of Chip-Last Fan-Out Panel Level Packaging with G2.5 LCD Facility Using FlexUPTM and Mechanical De-bonding Technologies , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).

[23]  N. Lee,et al.  Warpage and Thermal Characterization of Fan-Out Wafer-Level Packaging , 2017 .

[24]  V. N. Sekhar,et al.  Wafer level embedding technology for 3D wafer level embedded package , 2009, 2009 59th Electronic Components and Technology Conference.

[25]  Paulo Cardoso,et al.  Enabling of Fan-Out WLP for more demanding applications by introduction of enhanced dielectric material for higher reliability , 2014, 2014 IEEE 64th Electronic Components and Technology Conference (ECTC).

[26]  Alberto Martins,et al.  Development of Novel High Density System Integration Solutions in FOWLP-Complex and Thin Wafer-Level SiP and Wafer-Level 3D Packages , 2017, 2017 IEEE 67th Electronic Components and Technology Conference (ECTC).

[27]  P. Wu,et al.  The Development and the Integration of the 5 µm to 1 µm Half Pitches Wafer Level Cu Redistribution Layers , 2016, 2016 IEEE 66th Electronic Components and Technology Conference (ECTC).

[29]  J. Lau,et al.  Warpage Measurements and Characterizations of Fan-Out Wafer-Level Packaging With Large Chips and Multiple Redistributed Layers , 2018, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[30]  John H. Lau,et al.  Development of through silicon via (TSV) interposer technology for large die (21×21mm) fine-pitch Cu/low-k FCBGA package , 2009, 2009 59th Electronic Components and Technology Conference.

[31]  Eric Beyne,et al.  A Novel Fan-Out Concept for Ultra-High Chip-to-Chip Interconnect Density with 20-µm Pitch , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).

[32]  Benson Lin,et al.  A Novel System in Package with Fan-Out WLP for High Speed SERDES Application , 2016, 2016 IEEE 66th Electronic Components and Technology Conference (ECTC).

[33]  Hiroaki Kobayashi,et al.  Fan-Out Wafer-Level Packaging with highly flexible design capabilities , 2010, 3rd Electronics System Integration Technology Conference ESTC.

[34]  Zhaohui Chen,et al.  Drop Impact Reliability Test and Failure Analysis for Large Size High Density FOWLP Package on Package , 2017, 2017 IEEE 67th Electronic Components and Technology Conference (ECTC).

[35]  John H. Lau,et al.  3D IC Heterogeneous Integration by FOWLP , 2018 .

[36]  M. Wojnowski,et al.  3D eWLB — Horizontal and vertical interconnects for integration of passive components , 2013, 2013 IEEE 63rd Electronic Components and Technology Conference.

[37]  R. Hagen,et al.  Embedded Wafer Level Ball Grid Array (eWLB) , 2008, 2008 10th Electronics Packaging Technology Conference.

[38]  J. H. Lau,et al.  The Roles of DNP (Distance to Neutral point) on Solder Joint Reliability of Area Array Assemblies , 1997 .

[39]  Dan Oh,et al.  Low Cost Si-Less RDL Interposer Package for High Performance Computing Applications , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).

[40]  Curtis Zwenger,et al.  Chip Stackable, Ultra-thin, High-Flexibility 3D FOWLP (3D SWIFT® Technology) for Hetero-Integrated Advanced 3D WL-SiP , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).

[41]  J. Lau,et al.  Thermal management of 3D IC integration with TSV (through silicon via) , 2009, 2009 59th Electronic Components and Technology Conference.

[42]  J. Lau,et al.  Fan-Out Wafer-Level Packaging for Heterogeneous Integration , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).

[43]  K. Masu,et al.  SMAFTI packaging technology for new interconnect hierarchy , 2009, 2009 IEEE International Interconnect Technology Conference.

[44]  Douglas Yu,et al.  Analysis and Comparison of Thermal Performance of Advanced Packaging Technologies for State-of-the-Art Mobile Applications , 2016, 2016 IEEE 66th Electronic Components and Technology Conference (ECTC).

[45]  Koichi Tanaka,et al.  Development of Thinner POP Base Package by Die Embedded and RDL Structure , 2017 .

[46]  F. X. Che,et al.  Study on Process Induced Wafer Level Warpage of Fan-Out Wafer Level Packaging , 2016, 2016 IEEE 66th Electronic Components and Technology Conference (ECTC).

[47]  N. Takahashi,et al.  Vertical Integration of Stacked DRAM and High-Speed Logic Device Using SMAFTI Technology , 2009, IEEE Transactions on Advanced Packaging.

[48]  Hong Zhang,et al.  Novel Temporary Adhesive Materials for RDL-First Fan-Out Wafer-Level Packaging , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).

[49]  Andre Cardoso,et al.  Implementation of Keep-Out-Zones to Protect Sensitive Sensor Areas During Backend Processing in Wafer Level Packaging Technology , 2016, 2016 IEEE 66th Electronic Components and Technology Conference (ECTC).

[50]  Nicholas Kao,et al.  Warpage characterization of panel Fan-out (P-FO) package , 2014, 2014 IEEE 64th Electronic Components and Technology Conference (ECTC).

[51]  Jasmin Grosinger,et al.  A novel 3D packaging concept for RF powered sensor grains , 2014, 2014 IEEE 64th Electronic Components and Technology Conference (ECTC).

[52]  John Hunt,et al.  A Comparative Study of a Fan Out Packaged Product: Chip First and Chip Last , 2016, 2016 IEEE 66th Electronic Components and Technology Conference (ECTC).

[53]  R. Mahajan,et al.  Embedded Multi-die Interconnect Bridge (EMIB) -- A High Density, High Bandwidth Packaging Interconnect , 2016, 2016 IEEE 66th Electronic Components and Technology Conference (ECTC).

[54]  Fumihiko Taniguchi,et al.  Advanced Embedded Packaging for Power Devices , 2017, 2017 IEEE 67th Electronic Components and Technology Conference (ECTC).

[55]  Shin-Puu Jeng,et al.  3D Heterogeneous Integration with Multiple Stacking Fan-Out Package , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).

[56]  P. Ho,et al.  Reliability Assessment of Fan-Out Packages Using High Resolution Moiré Interferometry and Synchrotron X-Ray Microdiffraction , 2016, 2016 IEEE 66th Electronic Components and Technology Conference (ECTC).

[57]  Shin-Puu Jeng,et al.  Reliability evaluation of a CoWoS-enabled 3D IC package , 2013, 2013 IEEE 63rd Electronic Components and Technology Conference.

[58]  Sheng-Tsai Wu,et al.  Thermal Performance of 3D IC Integration with Through-Silicon Via (TSV) , 2011 .

[59]  Seung Wook Yoon,et al.  Fanout flipchip eWLB (embedded Wafer Level Ball Grid Array) technology as 2.5D packaging solutions , 2013, 2013 IEEE 63rd Electronic Components and Technology Conference.

[60]  J. Bauer,et al.  Large area compression molding for Fan-out Panel Level Packing , 2015, 2015 IEEE 65th Electronic Components and Technology Conference (ECTC).

[61]  M. Kao,et al.  Through-Silicon Hole Interposers for 3-D IC Integration , 2014, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[62]  C. Selvanayagam,et al.  Nonlinear Thermal Stress/Strain Analyses of Copper Filled TSV (Through Silicon Via) and Their Flip-Chip Microbumps , 2009, IEEE Transactions on Advanced Packaging.

[63]  Seung Wook Yoon,et al.  Advanced low profile PoP solution with embedded wafer level PoP (eWLB-PoP) technology , 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

[64]  M. Shih,et al.  Comparative Study on Mechanical and Thermal Performance of eWLB, M-Series™ and Fan-Out Chip Last Packages , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).

[65]  Yu-Min Lin,et al.  An RDL-First Fan-Out Panel-Level Package for Heterogeneous Integration Applications , 2019, 2019 IEEE 69th Electronic Components and Technology Conference (ECTC).

[66]  Vempati Srinivasa Rao,et al.  Development of High Density Fan Out Wafer Level Package (HD FOWLP) with Multi-layer Fine Pitch RDL for Mobile Applications , 2016, 2016 IEEE 66th Electronic Components and Technology Conference (ECTC).

[67]  John H. Lau,et al.  TSV manufacturing yield and hidden costs for 3D IC integration , 2010, 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC).

[68]  Douglas Yu,et al.  InFO (Wafer Level Integrated Fan-Out) Technology , 2016, 2016 IEEE 66th Electronic Components and Technology Conference (ECTC).

[69]  John H. Lau Patent issues of embedded fan-out wafer/panel level packaging , 2016, 2016 China Semiconductor Technology International Conference (CSTIC).

[70]  R. Aschenbrenner,et al.  Foldable Fan-Out Wafer Level Packaging , 2016, 2016 IEEE 66th Electronic Components and Technology Conference (ECTC).

[71]  Toshihide Suzuki,et al.  Integrated module structure of fan-out wafer level package for terahertz antenna , 2015, 2015 IEEE 65th Electronic Components and Technology Conference (ECTC).

[72]  Xuejun Fan,et al.  Finite-Element Analysis and Experimental Test for a Capped-Die Flip-Chip Package Design , 2016, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[73]  R. Chaware,et al.  Assembly and reliability challenges in 3D integration of 28nm FPGA die on a large high density 65nm passive interposer , 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

[74]  F. X. Che,et al.  Modeling and design solutions to overcome warpage challenge for fan-out wafer level packaging (FO-WLP) technology , 2015, 2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC).

[76]  Sam Peng,et al.  Warpage Tuning Study for Multi-chip Last Fan Out Wafer Level Package , 2017, 2017 IEEE 67th Electronic Components and Technology Conference (ECTC).

[77]  Steve Chiu,et al.  Development and characterization of new generation panel fan-out (P-FO) packaging technology , 2014, 2014 IEEE 64th Electronic Components and Technology Conference (ECTC).

[78]  Tim Olson,et al.  Adaptive Patterning Design Methodologies , 2016, 2016 IEEE 66th Electronic Components and Technology Conference (ECTC).

[79]  Chueh-An Hsieh,et al.  Fan-out technologies for WiFi SiP module packaging and electrical performance simulation , 2015, 2015 IEEE 65th Electronic Components and Technology Conference (ECTC).

[80]  Vinayak Pandey,et al.  Innovative Integration Solutions for SiP Packages Using Fan-Out Wafer Level eWLB Technology , 2017 .

[81]  Xuejun Fan,et al.  Wafer level packaging (WLP): Fan-in, fan-out and three-dimensional integration , 2010, 2010 11th International Thermal, Mechanical & Multi-Physics Simulation, and Experiments in Microelectronics and Microsystems (EuroSimE).

[82]  M. Tago,et al.  A novel "SMAFTI" package for inter-chip wide-band data transfer , 2006, 56th Electronic Components and Technology Conference 2006.

[83]  Ji-Jan Chen,et al.  Unified methodology for heterogeneous integration with CoWoS technology , 2013, 2013 IEEE 63rd Electronic Components and Technology Conference.

[84]  R. Weigel,et al.  3D rectangular waveguide integrated in embedded Wafer Level Ball Grid Array (eWLB) package , 2014, 2014 IEEE 64th Electronic Components and Technology Conference (ECTC).

[85]  B. Keser,et al.  The Redistributed Chip Package: A Breakthrough for Advanced Packaging , 2007, 2007 Proceedings 57th Electronic Components and Technology Conference.

[86]  M. Wojnowski,et al.  Novel embedded Z line (EZL) vertical interconnect technology for eWLB , 2015, 2015 IEEE 65th Electronic Components and Technology Conference (ECTC).

[88]  K. Soejima,et al.  A 3D Stacked Memory Integrated on a Logic Device Using SMAFTI Technology , 2007, 2007 Proceedings 57th Electronic Components and Technology Conference.

[89]  John H. Lau,et al.  Fan-Out Wafer-Level Packaging (FOWLP) of Large Chip with Multiple Redistribution-Layers (RDLs) , 2017 .

[90]  Tai Chong Chai,et al.  Development of Large Die Fine-Pitch Cu/Low- $k$ FCBGA Package With Through Silicon via (TSV) Interposer , 2011, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[91]  Tomohiro Nishiyama,et al.  System in wafer-level package technology with RDL-first process , 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

[92]  N. Lee,et al.  Warpage and Thermal Characterization of Fan-Out Wafer-Level Packaging , 2017, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[94]  Dale Ibbotson,et al.  Enabling the 2.5D Integration , 2012 .

[95]  Chen Kang,et al.  Advanced 3D eWLB-PoP (Embedded Wafer Level Ball Grid Array - Package on Package) Technology , 2016, 2016 IEEE 66th Electronic Components and Technology Conference (ECTC).

[96]  Kilsoo Kim,et al.  Study of Advanced Fan-Out Packages for Mobile Applications , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).

[97]  J. Bauer,et al.  From wafer level to panel level mold embedding , 2013, 2013 IEEE 63rd Electronic Components and Technology Conference.

[98]  John H. Lau Patent Issues of Fan-Out Wafer-Level Packaging , 2018 .

[99]  N. Lee,et al.  Design, Materials, Process, Fabrication, and Reliability of Fan-Out Wafer-Level Packaging , 2018, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[100]  John H. Lau,et al.  Fan-Out Wafer-Level Packaging , 2018 .

[101]  H. Hedler,et al.  An embedded device technology based on a molded reconfigured wafer , 2006, 56th Electronic Components and Technology Conference 2006.

[102]  B. Banijamali,et al.  Advanced reliability study of TSV interposers and interconnects for the 28nm technology FPGA , 2011, Electronic Components and Technology Conference.