On the testability of array structures for FFT computation

Presents new approaches for testing VLSI array architectures used in the computation of the complex N-point Fast Fourier Transform under a single combinational fault model. An unrestricted single cell-level fault model is considered. The first proposed approach is based on a process whose complexity is independent (or C- as constant) of the number of cells in the FFT architecture. This is accomplished by showing a topological equivalence between the FFT array and a linear (one-dimensional) array.<<ETX>>

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