Design and implementation of fault-tolerant soft processors on FPGAs

This paper presents a novel hardware mechanism to facilitate the design and implementation of soft processors on FPGAs using the Error-correcting code (ECC)-protected memory and Triple Modular Redundancy (TMR). Such techniques highly harden the fault tolerance of soft processors, especially their memories, which are the most radiation susceptible resources on FPGAs. This is demonstrated in the implementation of a fault-tolerant PicoBlaze processor on Xilinx FPGAs, in which we used an additional LookAhead technique to synchronize the processor with ECC-protected Block RAM (ECC BRAM). The resulting fault-tolerant PicoBlaze processor has the benefit of having a self-recoverable program memory in the presence of Single Error Upsets (SEUs), without halting the processor. Our techniques can be applied to other soft processors e.g. Xilinx MicroBlaze or Altera Nios.

[1]  Carl Carmichael,et al.  Triple Module Redundancy Design Techniques for Virtex FPGAs, Application Note 197 , 2001 .

[2]  M. Wirthlin,et al.  Fault Tolerant ICAP Controller for High-Reliable Internal Scrubbing , 2008, 2008 IEEE Aerospace Conference.

[3]  Tughrul Arslan,et al.  An FPGA task allocator with preliminary First-Fit 2D packing algorithms , 2011, 2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS).

[4]  Sandi Habinc,et al.  Dynamic Partial Reconfiguration in Space Applications , 2009, 2009 NASA/ESA Conference on Adaptive Hardware and Systems.

[5]  A. Lesea,et al.  The rosetta experiment: atmospheric soft error rate testing in differing technology FPGAs , 2005, IEEE Transactions on Device and Materials Reliability.

[6]  John M. Emmert,et al.  A survey of fault tolerant methodologies for FPGAs , 2006, TODE.

[7]  Mikel Azkarate-askasua,et al.  R3TOS: A reliable reconfigurable real-time operating system , 2010, 2010 NASA/ESA Conference on Adaptive Hardware and Systems.

[8]  Tughrul Arslan,et al.  Efficient On-Chip Task Scheduler and Allocator for Reconfigurable Operating Systems , 2011, IEEE Embedded Systems Letters.