Vertical Enhancement-Mode InAs Nanowire Field-Effect Transistor With 50-nm Wrap Gate

We present results on fabrication and dc characterization of vertical InAs nanowire wrap-gate field-effect transistor arrays with a gate length of 50 nm. The wrap gate is defined by evaporation of 50-nm Cr onto a 10-nm-thick HfO2 gate dielectric, where the gate is also separated from the source contact with a 100-nm SiOx, spacer layer. For a drain voltage of 0.5 V, we observe a normalized transconductance of 0.5 S/mm, a subthreshold slope around 90 mV/dec, and a threshold voltage just above 0 V. The highest observed normalized on current is 0.2 A/mm, with an off current of 0.2 mA/mm. These devices show a considerable improvement compared to previously reported vertical InAs devices with SiNx, gate dielectrics.

[1]  Lars Samuelson,et al.  One-dimensional heterostructures in semiconductor nanowhiskers , 2002 .

[2]  J. Plummer,et al.  Scaling theory for cylindrical, fully-depleted, surrounding-gate MOSFET's , 1997, IEEE Electron Device Letters.

[3]  Walter Riess,et al.  Realization of a silicon nanowire vertical surround-gate field-effect transistor. , 2006, Small.

[4]  B. Ryu,et al.  High performance 5nm radius Twin Silicon Nanowire MOSFET (TSNWFET) : fabrication on bulk si wafer, characteristics, and reliability , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[5]  Lars Samuelson,et al.  Epitaxial Growth of Indium Arsenide Nanowires on Silicon Using Nucleation Templates Formed by Self‐Assembled Organic Coatings , 2007 .

[6]  L. Wernersson,et al.  Vertical high mobility wrap-gated inas nanowire transistor , 2005, 63rd Device Research Conference Digest, 2005. DRC '05..

[7]  R. Chau,et al.  In search of "Forever," continued transistor scaling one new material at a time , 2005, IEEE Transactions on Semiconductor Manufacturing.

[8]  M. Meyyappan,et al.  Single Crystal Nanowire Vertical Surround-Gate Field-Effect Transistor , 2004 .

[9]  W. Prost,et al.  High Transconductance MISFET With a Single InAs Nanowire Channel , 2007, IEEE Electron Device Letters.

[10]  Charles M. Lieber,et al.  Growth of nanowire superlattice structures for nanoscale photonics and electronics , 2002, Nature.

[11]  Walter Riess,et al.  Vertical surround-gated silicon nanowire impact ionization field-effect transistors , 2007 .

[12]  R. Chau Benchmarking nanotechnology for high-performance and low-power logic transistor applications , 2004 .