Design of a low-power and low-cost booth-shift/add multiplexer-based multiplier

Design and implementation of a low-power and low-cost booth-shift/add multiplexer-based singed multiplier is presented. The main blocks of the circuit are constructed with some simple low-power structures. It includes multiplexer-based booth encoder and singed shifter blocks, multiplexer-based Manchester adder, an optimized and compact structure of control unit, and a low-power structure for full adder. The architecture has been successfully synthesized and verified using Xilinx ISE 11 and Spartan-3 FPGA. The results obtained by Xilinx Power Estimator (XPE) show that the proposed method has 58mW power consumption in 50MHz operation frequency.

[1]  N. Prasad,et al.  Implementation of Low Power and High Speed Multiplier-Accumulator Using SPST Adder and Verilog , 2012 .

[2]  Kavita Saharan.  Design and Implementation of an Efficient Modified Booth Multiplier using VHDL , 2013 .

[3]  Keshab K. Parhi,et al.  VLSI digital signal processing systems , 1999 .

[4]  Mónico Linares Aranda,et al.  CMOS Full-Adders for Energy-Efficient Arithmetic Applications , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[5]  Raghavendra B. Deshmukh,et al.  FPGA Implementation of Low Power Parallel Multiplier , 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).

[6]  G. D. Dalvi,et al.  Design and Implementation of High Performance Multiplier Using HDL , 2016 .

[7]  H. I. Saleh,et al.  An FPGA implementation guide for some different types of serial–parallel multiplier structures , 2000 .

[8]  Milos D. Ercegovac,et al.  High-level optimization techniques for low-power multiplier design , 2003 .

[9]  Bagyaveereswaran,et al.  Brauns Multiplier Implementation using FPGA with Bypassing Techniques , 2011, VLSIC 2011.

[11]  N. Thomas,et al.  Design and implementation of a high performance multiplier using HDL , 2012, 2012 International Conference on Computing, Communication and Applications.

[12]  Yingtao Jiang,et al.  Design and analysis of low-power 10-transistor full adders using novel XOR-XNOR gates , 2002 .

[13]  Jasbir Kaur.  Design and Implementation of an Efficient Modified Booth Multiplier using VHDL , 2013 .

[14]  Magdy Bayoumi,et al.  A novel high-performance CMOS 1-bit full-adder cell , 2000 .