Silicon Nanoelectronics: the Next 20 Years

According to Moore’s law, which predicts a decrease in feature sizes by a factor of 0.7 every 3 years, silicon transistors have become smaller and smaller in order to achieve higher integration densities, higher speed, lower power consumption and lower costs. This has been accomplished very successfully in the last 20 years, but will it continue in future? The latest ITRS, international technology roadmap for semiconductors (2001), describes in detail structural and electrical values for the scaling of CMOS down to the 22 nm node. Without any doubt, CMOS is considered to remain the mainstream technology for logic and memory. Many challenges have to be addressed for these CMOS generations regarding lithography, metallization, power dissipation and circuit design. Focusing on the device, the mandatory improvement in performance will be the key issue for further downscaling. Limitations arising from basic physical laws are still far away and will become important only well below sizes of ten nanometers.

[1]  M. Staedele.  Influence of Source-drain Tunneling on the Subthreshold Behavior of sub-10nm Double-gate MOSFETs , 2002, 32nd European Solid-State Device Research Conference.

[2]  J.D. Meindl,et al.  Ultra-large scale integration , 1984, IEEE Transactions on Electron Devices.

[3]  P. Vogl,et al.  Subband structure and mobility of two-dimensional holes in strained Si/SiGe MOSFET’s , 1998 .

[4]  H.-S. Philip Wong,et al.  Beyond the Conventional MOSFET , 2001 .

[5]  L. Dreeskornfeld,et al.  Perspectives of fully-depleted SOI transistors down to 20nm gate length , 2002, 2002 IEEE International SOI Conference.

[6]  H.-S.P. Wong,et al.  Extreme scaling with ultra-thin Si channel MOSFETs , 2002, Digest. International Electron Devices Meeting,.

[7]  Stoddart,et al.  Electronically configurable molecular-based logic gates , 1999, Science.

[8]  M. Haond,et al.  SON (Silicon-On-Nothing) P-MOSFETs with totally silicided (CoSi/sub 2/) polysilicon on 5 nm-thick Si-films: the simplest way to integration of metal gates on thin FD channels , 2002, Digest. International Electron Devices Meeting,.

[9]  Carbon nanotube electronics , 2002 .

[10]  Yasuo Takahashi,et al.  Size dependence of the characteristics of Si single-electron transistors on SIMOX substrates , 1996 .

[11]  B. Eitan,et al.  NROM: A novel localized trapping, 2-bit nonvolatile memory cell , 2000, IEEE Electron Device Letters.

[12]  Heung-Soo Im,et al.  Highly manufacturable 1 Gb NAND flash using 0.12 /spl mu/m process technology , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[13]  U. Langmann,et al.  50-nm vertical sidewall transistors with high channel doping concentrations , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

[14]  R.W. Keyes,et al.  Physical limits in digital electronics , 1975, Proceedings of the IEEE.

[15]  A. Grill,et al.  Strained Si NMOSFETs for high performance CMOS technology , 2001, 2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184).

[16]  W. Lai,et al.  The Vertical Replacement-Gate (VRG) MOSFET: a 50-nm vertical MOSFET with lithography-independent gate length , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[17]  R. J. Luyken,et al.  Concepts for hybrid CMOS-molecular non-volatile memories , 2003 .

[18]  H. Nayfeh,et al.  Strained silicon MOSFET technology , 2002, Digest. International Electron Devices Meeting,.

[19]  Franz Hofmann,et al.  Simulation of single electron circuits , 1995 .

[20]  Y. Toyoshima,et al.  14 nm gate length CMOSFETs utilizing low thermal budget process with poly-SiGe and Ni salicide , 2002, Digest. International Electron Devices Meeting,.

[21]  T. Tezuka,et al.  Design for scaled thin film strained-SOI CMOS devices with higher carrier mobility , 2002, Digest. International Electron Devices Meeting,.

[22]  Chenming Hu,et al.  Sub 50-nm FinFET: PMOS , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[23]  L. Risch,et al.  Vertical MOS Transistors with 70nm Channel Length , 1995, ESSDERC '95: Proceedings of the 25th European Solid State Device Research Conference.