Hysteresis in neural-type circuits

The mechanism of generation of hysteresis in a neural-type cell is presented. To make the theory tractable, it is assumed that the hysteresis determining MOS transistors operate in their square-law region when turned on. A set of equations is obtained that can be used for the design of MOS transistor neural-type cells which give pulse code modulation for the coding of information in neural-type systems.<<ETX>>