Implementing the Thread Programming Model on Hybrid FPGA/CPU Computational Components

Designers of embedded systems are constantly challenged to provide new capabilities to meet expanding requirements and increased computational needs at ever improving price/performance ratios. Recently emerging hybrid chips containing both CPU's and FPGA components have the potential to enjoy significant economies of scale, while enabling system designers to include a significant amount of specialization within the FPGA component. However, realizing the promise of these new hybrid chips will require programming models supporting a far more integrated view of the CPU and FPGA components than provided by current methods. This paper describes fundamental synchronization methods we are now developing for supporting a multi-threaded programming model that provides a transparent interface to the CPU and FPGA based component threads.