On the concept of dynamic multi-level simulation

This paper proposes a new concept dynamic multi-level simulation, also termed zooming, which may considerably enhance the speed and efficiency of simulation. The concept has been implemented and verified in RDV [GS84], an experimental prototype rule-based design verification system designed at Stanford University. 1 I N T R O D U C T I O N Simulation at a lower level such as gate-level is usually time consuming while functional simulation is faster but the results contain less detail. Conventional multi-level simulators have addressed this problem by permitting simulations at more than one level in the same environment. In ADLIB-SABLE [HD79, HDS0], gateand functional-level simulations may be carried out simultaneously. Circuit-level simulation in ADLIB-SABLE is difficult. Digital designs under verification in ADLIB-SABLE may be expressed in a hierarchical form [VW77,HDS0]. The designer then, based on the hierarchical tree, selects subparts of the design for verifying at different levels of detail. The DIANA [DH79] and SPLICE [NRA78] multi-level simulators permit mixed simulations at the gateand circuit-level. A problem associated with conventional multi-level simulators is that they are static. The decision on the level at which a component is verified is taken prior to initiating simulation and is based on the designer's experience, his intuition, or on the results of a previous simulation run. This can be often ineffective and uneconomical. 2 Z o o m V e r i f i c a t i o n A new approach dynamic multi-level simulation, as introduced in this paper, solves one of the problems associated with conventional multi-level simulators. In this approach, digital designs are expressed hierarchically. The top level of the hierarchy consists of a device whose input-output behavior is same as that of the design. The second level in the hierarchy consists of a collection of lower-level devices that constitute the design. Each of the devices, in turn, may be expressed as a collection of lower-level devices at the third level. If C 1 denotes the digital design at level 1, then, C 1 = C~,...,C~,..,Cn ~, where C~ is the i th constituent component at level 2, of C 1. C~ can be further expressed as C/z = C3 r~3 r~3 where Car is the r th constituent component at level 3, of C~. i l , " ' , ~ i r , " " ~ i l ~ ~Author's current address: Knowledge Systems Research, Room 4B-602, AT&T Bell Labs., Holmdel, NJ 07733. Tel. 201949-8689 Annual Simulation Symposium