Automatic generation of functional coverage models from CTL

Functional coverage models which measure the sufficiency of test stimuli are essential to the verification process. A key source of difficulty in their deployment emanates from the manual and imprecise nature of their development process and the lack of a sound measure of their quality. A functional coverage model can be considered complete only if it accurately reflects the behavior of the Design under Verification (DUV) as described in the specification. We present a method to automatically generate coverage models from a formal CTL description of design properties. Experimental results show that the functional coverage models generated using our technique correlate well with the detection of randomly injected errors into a design.

[1]  Boris Beizer,et al.  Software Testing Techniques , 1983 .

[2]  Kenneth L. McMillan,et al.  Symbolic model checking , 1992 .

[3]  Wolfgang Rosenstiel,et al.  Simulation-guided property checking based on multi-valued AR-automata , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[4]  Young-Il Kim,et al.  Systematic functional coverage metric synthesis from hierarchical temporal event relation graph , 2004, Proceedings. 41st Design Automation Conference, 2004..

[5]  Faisal Haque,et al.  Art of Verification with VERA , 2001 .

[6]  C. Eisner,et al.  Efficient Detection of Vacuity in ACTL Formulaas , 1997, CAV.

[7]  Ian G. Harris,et al.  Hardware-software covalidation: fault models and test generation , 2001, Sixth IEEE International High-Level Design Validation and Test Workshop.

[8]  Ian G. Harris,et al.  Fault models and test generation for hardware-software covalidation , 2003, IEEE Design & Test of Computers.

[9]  Faisal Imdad-Haque,et al.  The art of verification with Vera , 2001 .

[10]  Laurent Fournier,et al.  Functional verification methodology for microprocessors using the Genesys test-program generator , 1999, DATE '99.

[11]  Avi Ziv Cross-product functional coverage measurement with temporal properties-based assertions [logic verification] , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[12]  Thomas Kropf,et al.  Introduction to Formal Hardware Verification , 1999, Springer Berlin Heidelberg.

[13]  Avner Landver,et al.  Coverage-Directed Test Generation Using Symbolic Techniques , 1996, FMCAD.

[14]  James Monaco,et al.  Functional verification methodology for the PowerPC 604 microprocessor , 1996, DAC '96.

[15]  Adrian Evans,et al.  Functional verification of large ASICs , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[16]  Christian Berthet,et al.  Functional verification methodology of Chameleon processor , 1996, DAC '96.

[17]  D. Geist,et al.  A study in coverage-driven test generation , 1999, Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361).

[18]  Ian G. Harris,et al.  A method for the evaluation of behavioral fault models , 2003, Eighth IEEE International High-Level Design Validation and Test Workshop.

[19]  David A. Patterson,et al.  Computer Architecture: A Quantitative Approach , 1969 .

[20]  Alon Gluska Coverage-oriented verification of Banias , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[21]  M. Kantrowitz,et al.  I'm done simulating; now what? Verification coverage analysis and correctness checking of the DECchip 21164 Alpha microprocessor , 1996, 33rd Design Automation Conference Proceedings, 1996.

[22]  D. Abts,et al.  Verifying large-scale multiprocessors using an abstract verification environment , 1999, Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361).

[23]  Jian Shen,et al.  Functional verification of the Equator MAP1000 microprocessor , 1999, Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361).

[24]  Michael Kantrowitz,et al.  I'm done simulating; now what? Verification coverage analysis and correctness checking of the DEC chip 21164 Alpha microprocessor , 1996, DAC '96.

[25]  R. Raina,et al.  Functional verification methodology for the PowerPC 604 microprocessor , 1996, 33rd Design Automation Conference Proceedings, 1996.

[26]  D. Dill,et al.  Deriving a simulation input generator and a coverage metric from a formal specification , 2002, Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324).