Soft error vulnerability assessment of the real-time safety-related ARM Cortex-R5 CPU

This paper presents the results collected in a series of fault injection experiments conducted on a modern commercial embedded ARM Cortex-R5 processor, which is extensively used in real-time safety-related embedded applications. The paper aims to be a comprehensible study on how faults propagate through this CPU as they turn into errors at the core boundaries. The main goal of this study is to identify the most vulnerable parts in the micro-architecture of the ARM Cortex-R5 CPU. The long-term objective is to propose and decide how to protect these vulnerable parts without impacting the characteristic features of ARM processors: energy-efficiency and high-performance.

[1]  Riccardo Mariani,et al.  A flexible microcontroller architecture for fail-safe and fail-operational systems , 2010 .

[2]  Andreas Steininger,et al.  Software Composability and Mixed Criticality for Triple Modular Redundant Architectures , 2013, SASSUR@SAFECOMP.

[3]  Gurindar S. Sohi,et al.  Dynamic dead-instruction detection and elimination , 2002, ASPLOS X.

[4]  E. Normand.  Single event upset at ground level , 1996 .

[5]  Shubhendu S. Mukherjee,et al.  Measuring Architectural Vulnerability Factors , 2003, IEEE Micro.

[6]  Yong-Bin Kim,et al.  A 11-Transistor Nanoscale CMOS Memory Cell for Hardening to Soft Errors , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[7]  Narayanan Vijaykrishnan,et al.  Effect of Power Optimizations on Soft Error Rate , 2003, VLSI-SoC.

[8]  Renato J. O. Figueiredo,et al.  A Flexible Approach to Improving System Reliability with Virtual Lockstep , 2012, IEEE Transactions on Dependable and Secure Computing.

[9]  Emre Ozer,et al.  1 SEU and SET-tolerant ARM Cortex-R 4 CPU for Space and Avionics Applications , 2013 .

[10]  Carl E. Landwehr,et al.  Basic concepts and taxonomy of dependable and secure computing , 2004, IEEE Transactions on Dependable and Secure Computing.

[11]  Wei Liu,et al.  Using Register Lifetime Predictions to Protect Register Files Against Soft Errors , 2008 .

[12]  A. Johnston.  Scaling and Technology Issues for Soft Error Rates , 2000 .

[13]  Michael E. Wolf,et al.  The cache performance and optimizations of blocked algorithms , 1991, ASPLOS IV.

[14]  Shidhartha Das,et al.  A Triple Core Lock-Step (TCLS) ARM® Cortex®-R5 Processor for Safety-Critical and Ultra-Reliable Applications , 2016, 2016 46th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshop (DSN-W).

[16]  T. Calin,et al.  Upset hardened memory design for submicron CMOS technology , 1996 .

[17]  Shuguang Feng,et al.  Cost-efficient soft error protection for embedded microprocessors , 2006, CASES '06.