AN INVESTIGATION OF 3-D CURLED CHIP IN MACHINING-PART 2: SIMULATION AND VALIDATION USING FE TECHNIQUES

Abstract This paper presents a finite element modeling approach for the 3-D curled chip. Four different chip types, with varying complexities are modeled using this approach. The complexities include chip twist, serrations on the inner radius of the chip, thickness variation along the length of the chip, etc. The chip is treated as a 3-D elastic beam and the neutral axis of the chip is modeled as a 3-D spiral with instantaneously varying center and curl radius. Bending and shear stresses generated in the chip show very distinct patterns. Comparisons made between the mechanics-based and finite element models show good correlation in the magnitude and location of the failure stresses. The 3-D chip breaking pattern was also observed using high-speed filming techniques, and comparisons made between the FE model and experimental results show good correlation.