Influences of Substrate Pickup Integrated with the Source-End Engineering on ESD/Latch-Up Reliabilities in a 0.35-um 3.3-V Process

N-channel MOSFETs are often applied to the input/output ports as electrostatic discharge (ESD) protection elements, usually in the form of multi-finger placement. However, the non-uniform turned-on situation always occurred, therefore these sub-nMOSFETs can't conduct-on simultaneously. The ESD current will be passed through a few turned-on MOSFETs. It was due to the RBulk resistance of parasitic bipolar transistor for each finger transistor in silicon substrate is quite different. In this paper, the substrate P+ pickup and source-end engineering influences on ESD/latch-up (LU) capabilities of the input/ output ESD cells will be investigated. Here, the stripe number of P+ substrate pickup and different source-end layout manners will be carried out the important high-current snapback behaviors. Eventually, the It2 behaviour in a discrete distributed types (a full adding of P+ pickup stripe) in the source end is good (not good) for the ESD immunity.