Figures of merit for system path time estimation

A model to help in the evaluation of various technologies for large systems is presented. The space modeled is considered to be made up of a number of VLSI chips sufficient to comprise a CPU and cache arranged on a single planar package. The inputs consist of technology constraints and system design parameters. From these, a number of design characteristics are computed based on formulas derived from relationships observed in previous generations of large systems, and a system path-time figure of merit is then calculated. With some additional simplifying assumptions, several technology figures of merit can be derived. These include a measure of circuit density in circuits/ns/sup 2/, a generalized power-delay-cooling figure of merit, and a technology figure of merit involving the ratio of circuit delay to circuits/ns/sup 2/. The relationship of these to several existing chip and package technology figures of merit is also discussed.<<ETX>>