Galaxy: a high-performance energy-efficient multi-chip architecture using photonic interconnects
暂无分享,去创建一个
Nikolaos Hardavellas | John Kim | Gokhan Memik | Yan Pan | Seokwoo Song | Yigit Demir | N. Hardavellas | John Kim | G. Memik | Y. Demir | Yan Pan | Seokwoo Song
[1] Yuval Tamir,et al. Dynamically-Allocated Multi-Queue Buffers for VLSI Communication Switches , 1992, IEEE Trans. Computers.
[2] C L Schow,et al. 20-μm-pitch eight-channel monolithic fiber array coupling 160 Gb/s/channel to silicon nanophotonic chip , 2010, 2010 Conference on Optical Fiber Communication (OFC/NFOEC), collocated National Fiber Optic Engineers Conference.
[3] Kevin Skadron,et al. Temperature-aware microarchitecture , 2003, ISCA '03.
[4] Jung Ho Ahn,et al. Corona: System Implications of Emerging Nanophotonic Technology , 2008, 2008 International Symposium on Computer Architecture.
[5] Jung Ho Ahn,et al. McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).
[6] Karthikeyan Sankaralingam,et al. Dark Silicon and the End of Multicore Scaling , 2012, IEEE Micro.
[7] Jason Cong,et al. CMP network-on-chip overlaid with multi-band RF-interconnect , 2008, 2008 IEEE 14th International Symposium on High Performance Computer Architecture.
[8] Bruce Jacob,et al. DRAMSim2: A Cycle Accurate Memory System Simulator , 2011, IEEE Computer Architecture Letters.
[9] Christopher Batten,et al. Designing multi-socket systems using silicon photonics , 2009, ICS.
[10] M. Lipson,et al. Low loss etchless silicon photonic waveguides , 2009, 2009 Conference on Lasers and Electro-Optics and 2009 Conference on Quantum electronics and Laser Science Conference.
[11] Babak Falsafi,et al. Toward Dark Silicon in Servers , 2011, IEEE Micro.
[12] Thomas F. Wenisch,et al. SimFlex: Statistical Sampling of Computer System Simulation , 2006, IEEE Micro.
[13] Christopher Batten,et al. Implementing System-in-Package with Nanophotonic Interconnect , 2010 .
[14] Venkatesh Akella,et al. Addressing system-level trimming issues in on-chip nanophotonic networks , 2011, 2011 IEEE 17th International Symposium on High Performance Computer Architecture.
[15] K. Bernstein,et al. Scaling, power, and the future of CMOS , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..
[16] J. E. Cunningham,et al. High-efficiency hybrid III–V/Si external cavity DBR laser for 3-µm SOI waveguides , 2012, The 9th International Conference on Group IV Photonics (GFP).
[17] Ashok V. Krishnamoorthy,et al. Silicon-photonic network architectures for scalable, power-efficient multi-chip systems , 2010, ISCA '10.
[18] John Kim,et al. Exploring Benefits and Designs of Optically-Connected Disintegrated Processor Architecture , 2010 .
[19] Michael Yang,et al. A comparison of using icepak and flotherm in electronic cooling , 2000, ITHERM 2000. The Seventh Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.00CH37069).
[20] John Kim,et al. FeatherWeight: Low-cost optical arbitration with QoS support , 2011, 2011 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).
[21] Christopher Batten,et al. Silicon-photonic clos networks for global on-chip communication , 2009, 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip.
[22] William J. Dally,et al. Principles and Practices of Interconnection Networks , 2004 .
[23] Thomas F. Wenisch,et al. SimFlex: a fast, accurate, flexible full-system simulation framework for performance evaluation of server architecture , 2004, PERV.
[24] Christopher Batten,et al. Building Many-Core Processor-to-DRAM Networks with Monolithic CMOS Silicon Photonics , 2009, IEEE Micro.
[25] M. Horowitz,et al. A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS , 2007, IEEE Journal of Solid-State Circuits.
[26] Hui Chen,et al. Predictions of CMOS compatible on-chip optical interconnect , 2005, SLIP '05.
[27] Brian Rogers,et al. Scaling the bandwidth wall: challenges in and avenues for CMP scaling , 2009, ISCA '09.
[28] Ashok V. Krishnamoorthy,et al. Computer Systems Based on Silicon Photonic Interconnects A proposed supercomputer-on-a-chip with optical interconnections between processing elements will require development of new lower-energy optical components and new circuit architectures that match electrical datapaths to complementary optical , 2009 .
[29] J. Cunningham,et al. Optical proximity communication using reflective mirrors. , 2008, Optics express.
[30] Yu Zhang,et al. Firefly: illuminating future network-on-chip with nanophotonics , 2009, ISCA '09.
[31] Mikko H. Lipasti,et al. Light speed arbitration and flow control for nanophotonic interconnects , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).
[32] Chen Sun,et al. DSENT - A Tool Connecting Emerging Photonics with Electronics for Opto-Electronic Networks-on-Chip Modeling , 2012, 2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip.
[33] Scott Beamer,et al. Designing Multisocket Systems with Silicon Photonics , 2009 .