Shielding Logic Locking from Redundancy Attacks

The security of logic locking has been extensively examined under the threat model that assumes the availability of an activated IC. Recently, structural attacks such as ones based on redundancy analysis have challenged the viability of logic locking even when stringent measures are taken to preclude access to an activated IC. In this paper, we propose a gate selection based logic locking technique to identify key gate insertion sites such that the redundancy level deviates minimally under all key assignments. The proposed logic locking technique is evaluated on a set of benchmark circuits to confirm its resistance against redundancy analysis based attacks.

[1]  Sayak Ray,et al.  Evaluating the security of logic encryption algorithms , 2015, 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST).

[2]  Igor L. Markov,et al.  Protecting integrated circuits from piracy with test-aware logic locking , 2014, 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[3]  Jeyavijayan Rajendran,et al.  Security analysis of logic obfuscation , 2012, DAC Design Automation Conference 2012.

[4]  Jeyavijayan Rajendran,et al.  Provably-Secure Logic Locking: From Theory To Practice , 2017, CCS.

[5]  Jeyavijayan Rajendran,et al.  Security analysis of Anti-SAT , 2017, 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).

[6]  Jeyavijayan Rajendran,et al.  The cat and mouse in split manufacturing , 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

[7]  Joseph Zambreno,et al.  Preventing IC Piracy Using Reconfigurable Logic Barriers , 2010, IEEE Design & Test of Computers.

[8]  Farinaz Koushanfar,et al.  Active Hardware Metering for Intellectual Property Protection and Security , 2007, USENIX Security Symposium.

[9]  Premachandran R. Menon,et al.  Redundancy removal and simplification of combinational circuits , 1992, Digest of Papers. 1992 IEEE VLSI Test Symposium.

[10]  Ozgur Sinanoglu,et al.  SARLock: SAT attack resistant logic locking , 2016, 2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST).

[11]  Jeyavijayan Rajendran,et al.  Activation of logic encrypted chips: Pre-test or post-test? , 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[12]  Miron Abramovici,et al.  Low-cost redundancy identification for combinational circuits , 1994, Proceedings of 7th International Conference on VLSI Design.

[13]  Jarrod A. Roy,et al.  Ending Piracy of Integrated Circuits , 2010, Computer.

[14]  Alex Orailoglu,et al.  Piercing Logic Locking Keys through Redundancy Identification , 2019, 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[15]  Ankur Srivastava,et al.  Mitigating SAT Attack on Logic Locking , 2016, CHES.

[16]  Kwang-Ting Cheng.  On removing redundancy in sequential circuits , 1991, 28th ACM/IEEE Design Automation Conference.

[17]  Siddharth Garg,et al.  Logic Locking for Secure Outsourced Chip Fabrication: A New Attack and Provably Secure Defense Mechanism , 2017, ArXiv.

[18]  Jeyavijayan Rajendran,et al.  Removal Attacks on Logic Locking and Camouflaging Techniques , 2020, IEEE Transactions on Emerging Topics in Computing.

[19]  Jeyavijayan Rajendran,et al.  Fault Analysis-Based Logic Encryption , 2015, IEEE Transactions on Computers.