A low reference spur quadrature phase-locked loop for UWB systems

This paper presents a low phase noise and low reference spur quadrature phase-locked loop (QPLL) circuit that is implemented as a part of a frequency synthesizer for China UWB standard systems. A glitch-suppressed charge pump (CP) is employed for reference spur reduction. By forcing the phase frequency detector and CP to operate in a linear region of its transfer function, the linearity of the QPLL is further improved. With the proposed series-quadrature voltage-controlled oscillator, the phase accuracy of the QPLL is guaranteed. The circuit is fabricated in the TSMC 0.13 μm CMOS process and operated at 1.2-V supply voltage. The QPLL measures a phase noise of −95 dBc/Hz at 100-kHz offset and a reference spur of −71 dBc. The fully-integrated QPLL dissipates a current of 13 mA.

[1]  Young-Shig Choi,et al.  Gain-Boosting Charge Pump for Current Matching in Phase-Locked Loop , 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.

[2]  Shen-Iuan Liu,et al.  A spur-reduction technique for a 5-GHz frequency synthesizer , 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

[3]  B. Nauta,et al.  A 2.5-10-GHz clock multiplier unit with 0.22-ps RMS jitter in standard 0.18-/spl mu/m CMOS , 2004, IEEE Journal of Solid-State Circuits.

[4]  Shin-Il Lim,et al.  Charge pump with perfect current matching characteristics in phase-locked loops , 2000 .

[5]  F. Svelto,et al.  Analysis and Design of a Double-Quadrature CMOS VCO for Subharmonic Mixing at $Ka$-Band , 2008, IEEE Transactions on Microwave Theory and Techniques.

[6]  Roger Yubtzuan Chen,et al.  A High-speed Fast-acquisition CMOS Phase/Frequency Detector for MB-OFDM UWB , 2007, IEEE Transactions on Consumer Electronics.

[7]  L. Richard Carley,et al.  A 1-V, 1.4-2.5 GHz Charge-Pump-Less PLL for a Phase Interpolator Based CDR , 2007, 2007 IEEE Custom Integrated Circuits Conference.

[8]  Luca Larcher,et al.  Balanced CMOS LC-tank analog frequency dividers for quadrature LO generation , 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..

[9]  Wei-Liang Lee,et al.  A Spur Suppression Technique for Phase-Locked Frequency Synthesizers , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[10]  Hung-Ming Chien,et al.  A 4GHz Fractional-N synthesizer for IEEE 802.11a , 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).