An Output Matching Technique for a GaN Distributed Power Amplifier MMIC Using Tapered Drain Shunt Capacitors

This letter proposes an effective output matching technique using drain shunt capacitors with tapered capacitance values for a GaN distributed power amplifier MMIC to simultaneously obtain optimum load impedance for maximum output power of each transistor and phase velocity balance between input and output artificial transmission lines as well as length reduction of the transmission lines. To support its plausibility, a 2-6 GHz 10 W distributed power amplifier MMIC is designed and fabricated using a 0.25 μm GaN HEMT process of WIN Semiconductors. Measurement of the S parameters and CW output power demonstrates successful operation of the proposed technique in the design frequency range.