A power capping controller for multicore processors

This paper presents an online controller for tracking power-budgets in multicore processors using dynamic voltage-frequency scaling. The proposed control law comprises an integral controller whose gain is adjusted online based on the derivative of the power-frequency relationship. The control law is designed to achieve rapid settling time, and it's tracking property is formally proven. Importantly, the controller design does not require off-line analysis of application workloads making it feasible for emerging heterogeneous and asymmetric multicore processors. Simulation results are presented for controlling power dissipation in multiple cores of an asymmetric multicore processor. Each core is i) equipped with the controller, ii) assigned a power budget, and iii) operates independently in tracking to its power budget. We use a cycle-level multi-core simulator driven by traces from SPEC2006 benchmarks demonstrating that the proposed algorithm achieves a faster settling time than examples of a static setting of the controller gain.

[1]  R.W. Brodersen,et al.  A dynamic voltage scaled microprocessor system , 2000, IEEE Journal of Solid-State Circuits.

[2]  Uri C. Weiser,et al.  Performance, power efficiency and scalability of asymmetric cluster chip multiprocessors , 2006, IEEE Computer Architecture Letters.

[3]  Mark D. Hill,et al.  Amdahl's Law in the Multicore Era , 2008 .

[4]  David A. Patterson,et al.  Computer Architecture: A Quantitative Approach , 1969 .

[5]  Norman P. Jouppi,et al.  Heterogeneous chip multiprocessors , 2005, Computer.

[6]  Manuel Prieto,et al.  Maximizing Power Efficiency with Asymmetric Multicore Systems , 2009, ACM Queue.

[7]  Jung Ho Ahn,et al.  McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[8]  Soraya Ghiasi,et al.  System power management support in the IBM POWER6 microprocessor , 2007, IBM J. Res. Dev..

[9]  S. Naffziger,et al.  Power and temperature control on a 90-nm Itanium family processor , 2006, IEEE Journal of Solid-State Circuits.

[10]  Gabriel H. Loh,et al.  Zesto: A cycle-level simulator for highly detailed microarchitecture exploration , 2009, 2009 IEEE International Symposium on Performance Analysis of Systems and Software.

[11]  R.H. Katz,et al.  Tech Titans Building Boom , 2009, IEEE Spectrum.

[12]  Vanish Talwar,et al.  No "power" struggles: coordinated multi-level power management for the data center , 2008, ASPLOS.

[13]  Mahmut T. Kandemir,et al.  CPM in CMPs: Coordinated Power Management in Chip-Multiprocessors , 2010, 2010 ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis.

[14]  Sheng-Chih Lin,et al.  Cool Chips: Opportunities and Implications for Power and Thermal Management , 2008, IEEE Transactions on Electron Devices.

[15]  Max B Aron.  The single-chip cloud computer , 2010 .

[16]  Mark D. Hill,et al.  Amdahl's Law in the Multicore Era , 2008, Computer.

[17]  Jan M. Rabaey,et al.  Digital Integrated Circuits: A Design Perspective , 1995 .

[18]  Xiaorui Wang,et al.  Power capping: a prelude to power shifting , 2008, Cluster Computing.