OpenRAM: An open-source memory compiler

Computer systems research is often inhibited by the availability of memory designs. Existing Process Design Kits (PDKs) frequently lack memory compilers, while expensive commercial solutions only provide memory models with immutable cells, limited configurations, and restrictive licenses. Manually creating memories can be time consuming and tedious and the designs are usually inflexible. This paper introduces OpenRAM, an open-source memory compiler, that provides a platform for the generation, characterization, and verification of fabricable memory designs across various technologies, sizes, and configurations. It enables research in computer architecture, system-on-chip design, memory circuit and device research, and computer-aided design.

[1]  Zhiqiang Gao,et al.  A Flexible Embedded SRAM IP Compiler , 2007, 2007 IEEE International Symposium on Circuits and Systems.

[2]  Takayasu Sakurai,et al.  Highly Energy-Efficient SRAM With Hierarchical Bit Line Charge-Sharing Method Using Non-Selected Bit Line Charges , 2013, IEEE Journal of Solid-State Circuits.

[3]  Bharadwaj Amrutur,et al.  A replica technique for wordline and sense control in low-power SRAM's , 1998, IEEE J. Solid State Circuits.

[4]  Bai Na,et al.  An Efficient and Flexible Embedded Memory IP Compiler , 2012, 2012 International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery.

[5]  T. Sasaki,et al.  A 0.7V single-supply SRAM with 0.495um2 cell in 65nm technology utilizing self-write-back sense amplifier and cascaded bit line scheme , 2008, 2008 IEEE Symposium on VLSI Circuits.

[6]  Paul D. Franzon,et al.  FreePDK: An Open-Source Variation-Aware Design Kit , 2007, 2007 IEEE International Conference on Microelectronic Systems Education (MSE'07).

[7]  H. Morimura,et al.  A 1-V, 10-MHz, 3.5-mW, 1-Mb MTCMOS SRAM: with charge-recycling input/output buffers , 1999 .

[8]  Chein-Wei Jen,et al.  A high-level synthesizer for VLSI array architectures dedicated to digital signal processing , 1991, [Proceedings] ICASSP 91: 1991 International Conference on Acoustics, Speech, and Signal Processing.

[9]  Manfred Glesner,et al.  A CAD tool for designing large, fault-tolerant VLSI arrays , 1991, [1991] Proceedings. First Great Lakes Symposium on VLSI.

[10]  Wei Huang,et al.  A Flexible , Technology Adaptive Memory Generation Tool , 2006 .

[11]  Dave Johannsen,et al.  Bristle Blocks: A Silicon Compiler , 1979, 16th Design Automation Conference.

[12]  Sheng Wu,et al.  A 65nm embedded low power SRAM compiler , 2010, 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems.

[13]  Zheng Guo,et al.  Characterization of Dynamic SRAM Stability in 45 nm CMOS , 2011, IEEE Journal of Solid-State Circuits.

[14]  Masayuki Ohayashi,et al.  A 1.5-ns 256-kb BiCMOS SRAM with 60-ps 11-K logic gates , 1994 .

[15]  Youji Idei,et al.  A 1.5-ns access time, 78-μm2 memory-cell size, 64-kb ECL-CMOS SRAM , 1992 .

[16]  Robert W. Brodersen Anatomy of a Silicon Compiler , 1992 .

[17]  Tanmay Shah FabMem: A Multiported RAM and CAM Compiler for Superscalar Design Space Exploration. , 2010 .

[18]  E. Babayan,et al.  Synopsys' Educational Generic Memory Compiler , 2014, 10th European Workshop on Microelectronics Education (EWME).