Design and Evaluation of an Efficient Schmitt Trigger-Based Hardened Latch in CNTFET Technology

This paper presents a Schmitt trigger (ST) buffer using carbon nanotube FET (CNTFET) for reliable low-power applications. Nanoscale circuits are more susceptible to transient faults or soft errors due to the reduction of the stored charge in their sensitive nodes. Hereupon, low-cost and tolerant circuits design is a significant challenge, especially in the nanoscale storage cells. In addition, the proposed ST is utilized for designing a low-power hardened latch. In the proposed design, instead of up-sizing and increasing the input capacitance, the determined hysteresis mechanism of the proposed ST buffer is utilized to improve the single event upset hardness. The simulations are conducted based on the Stanford CNTFET model at 16-nm technology node. According to the results, the proposed ST has on average 90% lower power-delay product and higher robustness to PVT variations as compared to its most efficient CNTFET-based counterparts. Moreover, the simulations confirm the considerable tolerance of the proposed hardened latch to the multiple node upset as compared to the state-of-the-art designs. The proposed hardened latch has on average 68% higher critical charge, which considerably enhances its reliability and on average 16% smaller area as compared to its counterparts.

[1]  Fabrice Seguin,et al.  Soft Error Detection and Correction Technique for Radiation Hardening Based on C-element and BICS , 2014, IEEE Transactions on Circuits and Systems II: Express Briefs.

[2]  Kwanwoo Shin,et al.  Radiation hardness of the electrical properties of carbon nanotube network field effect transistors under high-energy proton irradiation , 2006, Nanotechnology.

[3]  Mahdi Fazeli,et al.  Single Event Multiple Upset (SEMU) Tolerant Latch Designs in Presence of Process and Temperature Variations , 2015, J. Circuits Syst. Comput..

[4]  Sheng Lin,et al.  Analysis and design of robust storage elements in nanometric circuits , 2011 .

[5]  Keivan Navi,et al.  Design and Evaluation of CNFET-Based Quaternary Circuits , 2012, Circuits, Systems, and Signal Processing.

[6]  Wei Zhang,et al.  A physical design tool for carbon nanotube field-effect transistor circuits , 2012, JETC.

[7]  Feng Ding,et al.  Chirality-specific growth of single-walled carbon nanotubes on solid alloy catalysts , 2014, Nature.

[8]  Don Walker,et al.  Single Event Effects in Carbon Nanotube-Based Field Effect Transistors Under Energetic Particle Radiation , 2014, IEEE Transactions on Nuclear Science.

[9]  SheXiao Xuan,et al.  SEU Hardened Flip-Flop Based on Dynamic Logic , 2013, IEEE Transactions on Nuclear Science.

[10]  H. Wong,et al.  Circuit-Level Performance Benchmarking and Scalability Analysis of Carbon Nanotube Transistor Circuits , 2009, IEEE Transactions on Nanotechnology.

[11]  Cristian Ravariu.  Semiconductor Materials Optimization for a TFET Device With Central Nothing Region on Insulator , 2013, IEEE Transactions on Semiconductor Manufacturing.

[12]  Cristian Ravariu.  The implementation methodology of the real effects in a NOI nanostructure, aided by simulation and modelling , 2010, Simul. Model. Pract. Theory.

[13]  Mahdi Fazeli,et al.  Low cost soft error hardened latch designs for nano-scale CMOS technology in presence of process variation , 2013, Microelectron. Reliab..

[14]  Fabrizio Lombardi,et al.  Design and Performance Evaluation of Radiation Hardened Latches for Nanoscale CMOS , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[15]  R.C. Baumann,et al.  Radiation-induced soft errors in advanced semiconductor technologies , 2005, IEEE Transactions on Device and Materials Reliability.

[16]  Said F. Al-Sarawi,et al.  Low power Schmitt trigger circuit , 2002 .

[17]  Keivan Navi,et al.  Design of energy-efficient and robust ternary circuits for nanotechnology , 2011, IET Circuits Devices Syst..

[18]  Lloyd W. Massengill,et al.  Impact of scaling on soft-error rates in commercial microprocessors , 2002 .

[19]  D. A. Bell,et al.  Solid State Pulse Circuits , 1976 .

[20]  Harold L. Hughes,et al.  Atomistic Modeling of Suspended Carbon Nanotube Field Effect Transistors Under Proton Radiation , 2015, IEEE Transactions on Nuclear Science.

[21]  Yong-bin Kim,et al.  Integrated Circuit Design Based on Carbon Nanotube Field Effect Transistor , 2011 .

[22]  Cristian Ravariu,et al.  Free carrier lifetime reduction in silicon by electron-beam irradiation , 2000, 2000 International Semiconductor Conference. 23rd Edition. CAS 2000 Proceedings (Cat. No.00TH8486).

[23]  Quming Zhou,et al.  Transistor sizing for radiation hardening , 2004, 2004 IEEE International Reliability Physics Symposium. Proceedings.

[24]  S. Mitra,et al.  Threshold Voltage and On–Off Ratio Tuning for Multiple-Tube Carbon Nanotube FETs , 2009, IEEE Transactions on Nanotechnology.

[25]  Paul H. Eaton,et al.  SEE characterization and mitigation in ultra-deep submicron technologies , 2009, 2009 IEEE International Conference on IC Design and Technology.

[26]  Massimo Alioto,et al.  Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial , 2012, IEEE Transactions on Circuits and Systems I: Regular Papers.

[27]  Yong-Bin Kim,et al.  CNTFET-Based Design of Ternary Logic Gates and Arithmetic Circuits , 2011, IEEE Transactions on Nanotechnology.

[28]  Fabrizio Lombardi,et al.  Design of a Nanometric CMOS Memory Cell for Hardening to a Single Event With a Multiple-Node Upset , 2014, IEEE Transactions on Device and Materials Reliability.

[29]  Kaushik Roy,et al.  Carbon Nanotube Electronics: Design of High-Performance and Low-Power Digital Circuits , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

[30]  Bahar Asgari,et al.  Design of Robust SRAM Cells Against Single-Event Multiple Effects for Nanometer Technologies , 2015, IEEE Transactions on Device and Materials Reliability.

[31]  H.-B Wang,et al.  An Area Efficient SEU-Tolerant Latch Design , 2014, IEEE Transactions on Nuclear Science.

[32]  Brian J Landi,et al.  Radiation Effects in Single-Walled Carbon Nanotube Thin-Film-Transistors , 2010, IEEE Transactions on Nuclear Science.

[33]  Somayeh Timarchi,et al.  An Ultra-Low-Power 9T SRAM Cell Based on Threshold Voltage Techniques , 2016, Circuits Syst. Signal Process..

[34]  Michel Steyaert,et al.  Novel cmos schmitt trigger , 1986 .

[35]  Fabrizio Lombardi,et al.  Design and Evaluation of Multiple Valued Logic Gates Using Pseudo N-Type Carbon Nanotube FETs , 2014, IEEE Transactions on Nanotechnology.

[36]  Yong-Bin Kim,et al.  Analysis and Design of Nanoscale CMOS Storage Elements for Single-Event Hardening With Multiple-Node Upset , 2012, IEEE Transactions on Device and Materials Reliability.

[37]  Yong-Bin Kim,et al.  Ultra-low voltage high-speed Schmitt trigger circuit in SOI MOSFET technology , 2007, IEICE Electron. Express.

[38]  Jie Deng,et al.  A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part II: Full Device Model and Circuit Performance Benchmarking , 2007, IEEE Transactions on Electron Devices.

[39]  B. Narasimham,et al.  Characterization of Digital Single Event Transient Pulse-Widths in 130-nm and 90-nm CMOS Technologies , 2007, IEEE Transactions on Nuclear Science.

[40]  Seth M. Hubbard,et al.  Radiation Effects in Carbon Nanoelectronics , 2012 .

[41]  Jie Zhang,et al.  Overcoming carbon nanotube variations through co-optimized technology and circuit design , 2011, 2011 International Electron Devices Meeting.

[42]  H.-S. Philip Wong,et al.  Carbon nanotube computer , 2013, Nature.

[43]  Hai Wei,et al.  Carbon nanotube circuit integration up to sub-20 nm channel lengths. , 2014, ACS nano.

[44]  Aminul Islam,et al.  Design of variation-resilient CNFET-based Schmitt trigger circuits with optimum hysteresis at 16-nm technology node , 2013, 2013 Annual IEEE India Conference (INDICON).

[45]  H. Wong,et al.  A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part I: Model of the Intrinsic Channel Region , 2007, IEEE Transactions on Electron Devices.

[46]  Yong-Bin Kim,et al.  Design of a Ternary Memory Cell Using CNTFETs , 2012, IEEE Transactions on Nanotechnology.

[47]  Ali Jalali,et al.  A Low-Power Multiplier Using an Efficient Single-Supply Voltage Level Converter , 2015, J. Circuits Syst. Comput..

[48]  Jan M. Rabaey,et al.  Digital Integrated Circuits: A Design Perspective , 1995 .