An analog VLSI array processor for classical and connectionist AI

The authors describe the architecture of an operational 31-cell CMOS VLSI Lukasiewicz logic array (LLA) which is regular, simple, area-efficient, and implemented with analog rather than digital processing elements. The prototype LLAs are programmed with input vectors derived from normal forms of sentences in the Lukasiewicz logic. This requires data inputs on the order of O(2/sup n/) for sentences in n implications, limits the size of the sentences that can be evaluated by a given LLA, and increases the number of pins needed on the VLSI package. The dual logic and algebraic semantics of Lukasiewicz logic allows LLAs to implement expert systems, neural networks and fuzzy logic functions. Schematic examples are given for each application, and results obtained by programming the prototype LLA as a fuzzy function generator show that the LLA implemented the notch function linearly, but with a slope that varied from that of the calculated function.<<ETX>>