Enhancing diagnosis resolution for delay defects based upon statistical timing and statistical fault models
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[1] Kaushik Roy,et al. Test challenges for deep sub-micron technologies , 2000, Proceedings - Design Automation Conference.
[2] Melvin A. Breuer,et al. Test generation for crosstalk-induced delay in integrated circuits , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).
[3] Robert C. Aitken,et al. Nanometer Technology Effects on Fault Models for IC Testing , 1999, Computer.
[4] Wei Jiang,et al. An economic model for integrated APC and SPC control charts , 2000 .
[5] Tracy Larrabee,et al. Diagnosing realistic bridging faults with single stuck-at information , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[6] D. E. Goldberg,et al. Genetic Algorithms in Search , 1989 .
[7] Kwang-Ting Cheng,et al. Delay defect diagnosis based upon statistical timing models - the first step [logic testing] , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.
[8] Kwang-Ting Cheng,et al. False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation , 2002, DAC '02.
[9] Keith Baker,et al. Defect-based delay testing of resistive vias-contacts a critical evaluation , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).
[10] Andrzej J. Strojwas,et al. Path delay fault diagnosis and coverage-a metric and an estimationtechnique , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[11] Melvin A. Breuer,et al. Digital systems testing and testable design , 1990 .
[12] A. Chatterjee,et al. Path-delay fault diagnosis in non-scan sequential circuits with at-speed test application , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).
[13] Melvin A. Breuer,et al. New Validation and Test Problems for High Performance Deep Sub-micron VLSI Circuits , 2000, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design.
[14] David E. Goldberg,et al. Genetic Algorithms in Search Optimization and Machine Learning , 1988 .
[15] Jing-Jia Liou,et al. False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation , 2002, Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324).
[16] Kwang-Ting Cheng,et al. Performance sensitivity analysis using statistical method and its applications to delay , 2000, ASP-DAC '00.
[17] Kwang-Ting Cheng,et al. Performance sensitivity analysis using statistical methods and its applications to delay testing , 2000, Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106).
[18] Kwang-Ting Cheng,et al. Pattern generation for delay testing and dynamic timing analysisconsidering power-supply noise effects , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[19] Hiroshi Takahashi,et al. A new method for diagnosing multiple stuck-at faults using multiple and single fault simulations , 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).
[20] Kwang-Ting Cheng,et al. Estimation for maximum instantaneous current through supply lines for CMOS circuits , 2000, IEEE Trans. Very Large Scale Integr. Syst..
[21] Kwang-Ting Cheng,et al. Delay Defect Diagnosis Based Upon Statistical Timing Models - The First Step , 2003, DATE.
[22] Patrick Girard,et al. A novel approach to delay-fault diagnosis , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.