On the SET/RESET current asymmetry in electrochemical metallization memory cells

Electrochemical metallization mem-ory (ECM) cells have attracted great attention due to their potential application as Resistive Random Access Memory (ReRAM) in future nonvolatile memories and logic circuits [1–3]. The digital information is encoded as different resist-ance states which can be programmed by applying appro-priate electrical stimuli. ECM cells typically consist of an active silver or copper electrode, an ion conducting switch-ing layer and an inert counter electrode. The switching mechanism in ECM cells relies on the electrochemical growth and dissolution of a copper or silver filament within the switching layer [1]. During SET operation a positive potential is applied to the active electrode and the active silver/copper electrode is oxidized. The correspond-ing cations migrate towards the counter electrode. A reduc-tion occurs at the counter electrode and a silver/copper filament subsequently grows towards the active electrode. As soon as an electronic contact is achieved, e.g. by the onset of electron tunneling between the filament and the active electrode, the resistance drops to the low resistive state (LRS) [4]. By tuning the current limitation during the SET operation different LRS can be programmed accord-ing to the empirical law

[1]  E. Vianello,et al.  Experimental Investigation and Empirical Modeling of the Set and Reset Kinetics of Ag-GeS2 Conductive Bridging Memories , 2012, 2012 4th IEEE International Memory Workshop.

[2]  Gaston H. Gonnet,et al.  On the LambertW function , 1996, Adv. Comput. Math..

[3]  Shimeng Yu,et al.  Compact Modeling of Conducting-Bridge Random-Access Memory (CBRAM) , 2011, IEEE Transactions on Electron Devices.

[4]  P. Gonon,et al.  Back-end-of-line compatible Conductive Bridging RAM based on Cu and SiO2 , 2011 .

[5]  M. Kozicki,et al.  Cation-based resistance change memory , 2013 .

[6]  S. Menzel,et al.  Analytical analysis of the generic SET and RESET characteristics of electrochemical metallization memory cells. , 2013, Nanoscale.

[7]  Robert K. Henderson,et al.  A 3×3, 5µm pitch, 3-transistor single photon avalanche diode array with integrated 11V bias generation in 90nm CMOS technology , 2010, 2010 International Electron Devices Meeting.

[8]  Rainer Waser,et al.  Switching kinetics of electrochemical metallization memory cells. , 2013, Physical chemistry chemical physics : PCCP.

[9]  J. Simmons Generalized Formula for the Electric Tunnel Effect between Similar Electrodes Separated by a Thin Insulating Film , 1963 .

[10]  R. Waser,et al.  Resistive switching in electrochemical metallization memory cells , 2009 .

[11]  Yuhong Kang,et al.  Physics of the Voltage Constant in Multilevel Switching of Conductive Bridge Resistive Memory , 2013 .

[12]  T. Hasegawa,et al.  Atomic Switch: Atom/Ion Movement Controlled Devices for Beyond Von‐Neumann Computers , 2012, Advanced materials.

[13]  S. Menzel,et al.  Simulation of multilevel switching in electrochemical metallization memory cells , 2012 .