3D IC test scheduling using simulated annealing

Three-dimensional integrated circuits (3D ICs) have many advantages over traditional integrated circuits. Although 3D ICs have such advantages, there are many difficulties to be overcome. Testing for 3D ICs is regarded as the most difficult challenge. High power density in 3D ICs causes rising temperature, which may cause test yield loss. In this paper, we propose a thermal-aware test scheduling technique for 3D ICs. Our experimental results show that the maximum temperature in the test schedule of our proposed technique is under the temperature limit while the test length overhead is only 19%.

[1]  Kevin Skadron,et al.  Temperature-aware microarchitecture: Modeling and implementation , 2004, TACO.

[2]  Krishnendu Chakrabarty,et al.  Precedence-based, preemptive, and power-constrained test scheduling for system-on-a-chip , 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

[3]  Gabriel H. Loh,et al.  Thermal analysis of a 3D die-stacked high-performance microprocessor , 2006, GLSVLSI '06.

[4]  A.M. Davis,et al.  Microelectronic circuits , 1983, Proceedings of the IEEE.

[5]  Krishnendu Chakrabarty.  Test scheduling for core-based systems , 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

[6]  Parameswaran Ramanathan,et al.  Power and Thermal Constrained Test Scheduling Under Deep Submicron Technologies , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[7]  A. Sedra.  Microelectronic circuits , 1982 .

[8]  Yervant Zorian,et al.  Testing 3D chips containing through-silicon vias , 2009, 2009 International Test Conference.

[9]  Anantha Chandrakasan,et al.  Timing, energy, and thermal performance of three-dimensional integrated circuits , 2004, GLSVLSI '04.

[10]  Erik Jan Marinissen,et al.  Optimization methods for post-bond die-internal/external testing in 3D stacked ICs , 2010, 2010 IEEE International Test Conference.

[11]  Robert S. Patti,et al.  Three-Dimensional Integrated Circuits and the Future of System-on-Chip Designs , 2006, Proceedings of the IEEE.

[12]  Li Shang,et al.  Three-dimensional multiprocessor system-on-chip thermal optimization , 2007, 2007 5th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

[13]  Kaustav Banerjee,et al.  Full chip thermal analysis of planar (2-D) and vertically integrated (3-D) high performance ICs , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

[14]  H. Fujiwara,et al.  Thermal-Safe Test Access Mechanism and Wrapper Co-optimization for System-on-Chip , 2007, 16th Asian Test Symposium (ATS 2007).

[15]  Jian Xu,et al.  Demystifying 3D ICs: the pros and cons of going vertical , 2005, IEEE Design & Test of Computers.

[16]  Krishnendu Chakrabarty,et al.  Thermal-Safe Test Scheduling for Core-Based System-on-Chip Integrated Circuits , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[17]  Krishnendu Chakrabarty,et al.  Test scheduling for core-based systems using mixed-integer linearprogramming , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[18]  Mario H. Konijnenburg,et al.  A structured and scalable test access architecture for TSV-based 3D stacked ICs , 2010, 2010 28th VLSI Test Symposium (VTS).

[19]  Chunsheng Liu,et al.  Thermal-aware test scheduling and hot spot temperature minimization for core-based systems , 2005, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05).