New theoretical results on quadratic placement

Current tools for VLSI placement are based either on quadratic placement, or on min-cut heuristics, or on simulated annealing. For the most complex chips with millions of movable objects, algorithms based on quadratic placement seem to yield the best results within reasonable time. In this paper, we prove several new theoretical results on quadratic placement. We point out connections to random walks and electrical networks. Moreover, we argue that quadratic placement has, in contrast to the other approaches, some well-defined stability properties. Finally, we consider the question how to choose the weights of the clique edges representing a multiterminal net optimally.

[1]  David S. Johnson,et al.  Some Simplified NP-Complete Graph Problems , 1976, Theor. Comput. Sci..

[2]  Jens Vygen,et al.  Algorithms for large-scale flat placement , 1997, DAC.

[3]  Sudipto Guha,et al.  Improved approximations of crossings in graph drawings , 2000, STOC '00.

[4]  Andrew B. Kahng,et al.  Spectral Partitioning with Multiple Eigenvectors , 1999, Discret. Appl. Math..

[5]  James B. Orlin A Faster Strongly Polynomial Minimum Cost Flow Algorithm , 1993, Oper. Res..

[6]  W. T. Tutte How to Draw a Graph , 1963 .

[7]  Georg Sigl,et al.  GORDIAN: VLSI placement by quadratic programming and slicing optimization , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  Ulrich Brenner,et al.  Faster and better global placement by a new transportation algorithm , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[9]  Charles M. Fiduccia,et al.  A linear-time heuristic for improving network partitions , 1988, 25 years of DAC.

[10]  Jens Vygen Plazierung im VLSI-Design und ein zweidimensionales Zerlegungsproblem , 1996 .

[11]  David Pisinger,et al.  Local Search for Final Placement in VLSI Design , 2001, ICCAD.

[12]  David S. Johnson,et al.  The Rectilinear Steiner Tree Problem is NP Complete , 1977, SIAM Journal of Applied Mathematics.

[13]  Satish Rao,et al.  New Approximation Techniques for Some Linear Ordering Problems , 2005, SIAM J. Comput..

[14]  Satish Rao,et al.  New approximation techniques for some ordering problems , 1998, SODA '98.

[15]  Frank M. Johannes,et al.  Generic global placement and floorplanning , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[16]  M. Breuer,et al.  Correction to 'A Force Directed Component Placement Procedure for Printed Circuit Boards' , 1980 .

[17]  Dorothea Wagner,et al.  Modeling Hypergraphs by Graphs with the Same Mincut Properties , 1993, Inf. Process. Lett..

[18]  Jens Vygen,et al.  Worst-case ratios of networks in the rectilinear plane , 2001, Networks.

[19]  Miklós Ajtai Recursive construction for 3-regular expanders , 1994, Comb..

[20]  Andrew B. Kahng,et al.  Recent directions in netlist partitioning: a survey , 1995, Integr..

[21]  Robert Krauthgamer,et al.  A Polylogarithmic Approximation of the Minimum Bisection , 2006, SIAM Rev..

[22]  Dennis J.-H. Huang,et al.  Quadratic Placement Revisited , 1997, Proceedings of the 34th Design Automation Conference.

[23]  Prabhakar Raghavan,et al.  Random walks on weighted graphs and applications to on-line algorithms , 1993, JACM.

[24]  Sudipto Guha,et al.  Improved Approximations of Crossings in Graph Drawings and VLSI Layout Areas , 2002, SIAM J. Comput..

[25]  Santosh S. Vempala Random projection: a new approach to VLSI layout , 1998, Proceedings 39th Annual Symposium on Foundations of Computer Science (Cat. No.98CB36280).

[26]  D. F. Wong,et al.  Simulated Annealing for VLSI Design , 1988 .

[27]  Jens Vygen,et al.  On dual minimum cost flow algorithms , 2002, Math. Methods Oper. Res..

[28]  Carl Sechen,et al.  VLSI Placement and Global Routing Using Simulated Annealing , 1988 .

[29]  Joel E. Cohen,et al.  Paradoxical behaviour of mechanical and electrical networks , 1991, Nature.

[30]  Clifford J. Fisk,et al.  “ACCEL” automated circuit card etching layout , 1965, DAC.

[31]  J. Laurie Snell,et al.  Random Walks and Electric Networks: PREFACE , 1984 .

[32]  Curt Jones,et al.  Finding Good Approximate Vertex and Edge Partitions is NP-Hard , 1992, Inf. Process. Lett..

[33]  Joseph Naor,et al.  Divide-and-conquer approximation algorithms via spreading metrics , 1995, Proceedings of IEEE 36th Annual Foundations of Computer Science.

[34]  Thomas Lengauer,et al.  Combinatorial algorithms for integrated circuit layout , 1990, Applicable theory in computer science.

[35]  Miklós Ajtai,et al.  Recursive construction for 3-regular expanders , 1987, 28th Annual Symposium on Foundations of Computer Science (sfcs 1987).

[36]  Peter G. Doyle,et al.  Random Walks and Electric Networks: REFERENCES , 1987 .

[37]  N. Quinn,et al.  A forced directed component placement procedure for printed circuit boards , 1979 .

[38]  Christos D. Zaroliagis,et al.  Computing Mimicking Networks , 1998, ICALP.

[39]  S.,et al.  An Efficient Heuristic Procedure for Partitioning Graphs , 2022 .

[40]  M. Hestenes,et al.  Methods of conjugate gradients for solving linear systems , 1952 .

[41]  Jens Vygen,et al.  Geometric quadrisection in linear time, with application to VLSI placement , 2005, Discret. Optim..

[42]  Charles J. Alpert,et al.  Spectral Partitioning: The More Eigenvectors, The Better , 1995, 32nd Design Automation Conference.