Abstract This paper presents the design, the mixed simulation and the implementation of an original FPGA embedded impedance analyser. This system is specially dedicated to piezo sensors and piezo transducers (audio and ultrasonic bands up to 10 MHz). The specificity of this SOPC is to avoid the measurement of the current through the impedance Z . The output resistance of the excitation generator V G is a numerical resistive network RG. This network is feedback controlled in order to maintain the impedance voltage at V G / 2 . The phase φ of this voltage is measured by synchronous detection. Real and imaginary parts of Z are determinated from RG and φ during a fast frequential sweep. The range of analysis is managed by a high accuracy DDS synthesizer. All the numerical architecture is implemented in a FPGA Stratix II board. Its design is done by using SimPowerSystems and Altera-DSP Builder tools. The architecture is validated by HIL simulation, in which the piezo transducer is modeled by a Butterworth van Dycke (BVD) structure. The system is tested within the bandwidth [1.8 MHz–2.8 MHz] with a 20 mm square ceramic resonant at 2 MHz.
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