A CPL-based dual supply 32-bit ALU for sub 180 nm CMOS technologies
暂无分享,去创建一个
[1] Yu Cao,et al. New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation , 2000, Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044).
[2] M. Sachdev,et al. Dual supply voltage clocking for 5 GHz 130 nm integer execution core , 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).
[3] Steven Hsu,et al. Effectiveness and scaling trends of leakage control techniques for sub-130nm CMOS technologies , 2003, ISLPED '03.
[4] 藤田 哲也,et al. A 0.9V 150MHz 10mW 4mm^2 2-D Discrete Cosine Transform Core Processor with Variable Threshold-Voltage (VT) Scheme , 1996 .
[5] Kaushik Roy,et al. High-performance low-power CMOS circuits using multiple channel length and multiple oxide thickness , 2000, Proceedings 2000 International Conference on Computer Design.
[6] T. Kuroda. CMOS design challenges to power wall , 2001, Digest of Papers. Microprocesses and Nanotechnology 2001. 2001 International Microprocesses and Nanotechnology Conference (IEEE Cat. No.01EX468).
[7] Mircea R. Stan. Optimal Voltages and Sizing for Low Power , 1999 .
[8] Hiroshi Kawaguchi,et al. Low-power CMOS design through VTH control and low-swing circuits , 1997, ISLPED '97.
[9] K. Soumyanath,et al. Sub-500-ps 64-b ALUs in 0 . 18-m SOI / Bulk CMOS : Design and Scaling Trends , 2001 .
[10] T. Fujita,et al. A 0.9 V 150 MHz 10 mW 4 mm/sup 2/ 2-D discrete cosine transform core processor with variable-threshold-voltage scheme , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.
[11] William J. Bowhill,et al. Design of High-Performance Microprocessor Circuits , 2001 .