Technologies and reliability of modern embedded flash cells

Abstract We have examined the various technologies for implementing embedded flash cells. We discuss the technological basics with regard to practical consequences and concentrate on the aspects of reliability of embedded flash cells. The main focus is automotive application because they pose extremely hard requirements in terms of ambient parameters, life-time and programming cycles. Our work is mainly composed of three different parts. The first part gives an insight into the basic technology of embedded flash memory. It specifically concentrates on floating gate devices, which dominate today’s products. This first part is based on a broad analysis of scientific literature and describes the state of the art. The required process steps are presented as well as the test approaches to ensure a high-quality production level. In the second part an overview is given about products actually on the market. Based on this information, the technological characteristics of the different cell architectures are discussed in the third part.

[1]  Gabriella Ghidini,et al.  Floating gate memories reliability , 1992 .

[2]  K. Eikyu,et al.  A quantitative analysis of time-decay reproducible stress-induced leakage current in SiO/sub 2/ films , 1997 .

[3]  A. Hoefler,et al.  Statistical modeling of the program/erase cycling acceleration of low temperature data retention in floating gate nonvolatile memories , 2002, 2002 IEEE International Reliability Physics Symposium. Proceedings. 40th Annual (Cat. No.02CH37320).

[4]  David Burnett,et al.  A reliability methodology for low temperature data retention in floating gate non-volatile memories , 2001, 2001 IEEE International Reliability Physics Symposium Proceedings. 39th Annual (Cat. No.00CH37167).

[5]  Yu Wang,et al.  An analytical retention model for SONOS nonvolatile memory devices in the excess electron state , 2005 .

[6]  U. Sharma,et al.  Improved performance and reliability of split gate source-side injected flash memory cells , 1996, International Electron Devices Meeting. Technical Digest.

[7]  Jelke Dijkstra,et al.  Reliability implications in advanced embedded two-transistor-Fowler–Nordheim-NOR flash memory devices , 2002 .

[8]  Giovanni Campardo,et al.  An overview of flash architectural developments , 2003 .

[9]  B. Eitan,et al.  Hot-electron injection into the oxide in n-channel MOS devices , 1981, IEEE Transactions on Electron Devices.

[10]  Dirk Wellekens,et al.  Failure Rate Prediction and Accelerated Detection of Anomalous Charge Loss in Flash Memories by Using an Analytical Transient Physics-Based Charge Loss Model. , 2002 .

[11]  R. S. Scott,et al.  Thickness dependence of stress-induced leakage currents in silicon oxide , 1997 .

[12]  William D. Brown,et al.  Nonvolatile Semiconductor Memory Technology , 1997 .

[13]  N. Ajika,et al.  Identification of stress-induced leakage current components and the corresponding trap models in SiO/sub 2/ films , 1997 .

[14]  Kuniyoshi Yoshikawa,et al.  Degradation mechanism of flash EEPROM programming after program/erase cycles , 1993, Proceedings of IEEE International Electron Devices Meeting.

[15]  Chenming Hu.  Nonvolatile semiconductor memories : technologies, design, and applications , 1991 .

[16]  B. Eitan,et al.  Electrons retention model for localized charge in oxide-nitride-oxide (ONO) dielectric , 2002, IEEE Electron Device Letters.

[17]  Y. Moriyama,et al.  A 0.9 V operation 2-transistor flash memory for embedded logic LSIs , 1999, 1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325).

[18]  C. Hu,et al.  Stress-induced current in thin silicon dioxide films , 1992, 1992 International Technical Digest on Electron Devices Meeting.

[19]  C.T. Swift,et al.  An embedded 90 nm SONOS nonvolatile memory utilizing hot electron programming and uniform tunnel erase , 2002, Digest. International Electron Devices Meeting,.

[20]  R. Muller,et al.  A unified model for hot-electron currents in MOSFET's , 1981, 1981 International Electron Devices Meeting.

[21]  C. Hu.  Lucky-electron model of channel hot electron emission , 1979, 1979 International Electron Devices Meeting.

[22]  Dirk Wellekens,et al.  Embedded HIMOS(R) flash memory in 0.35 /spl mu/m and 0.25 /spl mu/m CMOS technologies , 2000 .

[23]  R. Rajsuman,et al.  Iddq testing for CMOS VLSI , 1994, Proceedings of the IEEE.

[24]  Andrea L. Lacaita,et al.  Modeling of anomalous SILC in flash memories based on tunneling at multiple defects , 2002 .

[25]  Piero Olivo,et al.  Flash memory cells-an overview , 1997, Proc. IEEE.

[26]  Piero Olivo,et al.  Overerase phenomena: an insight into flash memory reliability , 2003, Proc. IEEE.

[27]  R. Bez,et al.  Advanced flash memory reliability , 2004, 2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866).