A Quantization Error Minimization Method Using DDS-DAC for Wideband Fractional-N Frequency Synthesizer

This paper presents a technique to reduce the quantization error in fractional division for a wideband fractional-N frequency synthesizer. By using a direct digital synthesis phase accumulator as the fractional divider and a DAC as the phase-to-pulse converter, the quantization error can be much smaller than the one by conventional sigma-delta modulated multi-modulus divider. With small quantization error, a dedicated compensation mechanism is no longer necessary for wide loop bandwidth applications. To demonstrate this concept, a prototype chip was implemented with 0.18-μm CMOS. The synthesizer consumes 19 mA from a 1.8 V supply. With 1 MHz closed-loop bandwidth, the in-band noise is -98 dBc/Hz and the 3 MHz offset noise is -122 dBc/Hz for a 1.8 GHz output. The output exhibited 27 dB phase noise reduction compared to the generic sigma-delta structure. The settling time is 2 μs under a 35 MHz frequency step.

[1]  Lars C. Jansson,et al.  A wideband 2.4-GHz delta-sigma fractional-NPLL with 1-Mb/s in-loop modulation , 2004, IEEE Journal of Solid-State Circuits.

[2]  M.H. Perrott,et al.  A 1-MHZ bandwidth 3.6-GHz 0.18-/spl mu/m CMOS fractional-N synthesizer utilizing a hybrid PFD/DAC structure for reduced broadband phase noise , 2006, IEEE Journal of Solid-State Circuits.

[3]  M. Steyaert,et al.  A CMOS monolithic ΔΣ-controlled fractional-N frequency synthesizer for DCS-1800 , 2002, IEEE J. Solid State Circuits.

[4]  Waleed Khalil,et al.  A 1 MHz Bandwidth, 6 GHz 0.18 µm CMOS Type-I ΔΣ Fractional-NSynthesizer for WiMAX Applications , 2009, IEEE J. Solid State Circuits.

[5]  Shin-Il Lim,et al.  Charge pump with perfect current matching characteristics in phase-locked loops , 2000 .

[6]  R. Castello,et al.  A 700-kHz bandwidth /spl Sigma//spl Delta/ fractional synthesizer with spurs compensation and linearization techniques for WCDMA applications , 2004, IEEE Journal of Solid-State Circuits.

[7]  H. Samueli,et al.  An Analysis of the Output Spectrum of Direct Digital Frequency Synthesizers in the Presence of Phase-Accumulator Truncation , 1987, 41st Annual Symposium on Frequency Control.

[8]  M. A. Copeland,et al.  Delta-Sigma Modulation in , 1993 .

[9]  K.J. Wang,et al.  A Wide-Bandwidth 2.4GHz ISM-Band Fractional-N PLL with Adaptive Phase-Noise Cancellation , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[10]  Beomsup Kim,et al.  A 14-b direct digital frequency synthesizer with sigma-delta noise shaping , 2004, IEEE Journal of Solid-State Circuits.

[11]  A. N. Willson,et al.  Analysis of the output spectrum for direct digital frequency synthesizers in the presence of phase truncation and finite arithmetic precision , 2001, ISPA 2001. Proceedings of the 2nd International Symposium on Image and Signal Processing and Analysis. In conjunction with 23rd International Conference on Information Technology Interfaces (IEEE Cat..

[12]  Bang-Sup Song,et al.  A 1.8GHz Spur-Cancelled Fractional-N Frequency Synthesizer with LMS-Based DAC Gain Calibration , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.