A high performance hardware architecture for portable, low-power retinal vessel segmentation

Abstract The retina of the human eye and more particularly the retinal blood vasculature can be used in several medical and biometric applications. The use of retinal images in such applications however, is computationally intensive, due to the high complexity of the algorithms used to extract the vessels from the retina. In addition, the emergence of portable biometric authentication applications, as well as onsite biomedical diagnostics raises the need for real-time, power-efficient implementations of such algorithms that can also satisfy the performance and accuracy requirements of portable systems that use retinal images. In an attempt to meet those requirements, this work presents a VLSI implementation of a retina vessel segmentation system while exploring various parameters that affect the power consumption, the accuracy and performance of the system. The proposed design implements an unsupervised vessel segmentation algorithm which utilizes matched filtering with signed integers to enhance the difference between the blood vessels and the rest of the retina. The design accelerates the process of obtaining a binary map of the vessels tree by using parallel processing and efficient resource sharing, achieving real-time performance. The design has been verified on a commercial FPGA platform and exhibits significant performance improvements (up to 90×) when compared to other existing hardware and software implementations, with an overall accuracy of 92.4%. Furthermore, the low power consumption of the proposed VLSI implementation enables the proposed architecture to be used in portable systems, as it achieves an efficient balance between performance, power consumption and accuracy.