An accurate model for soft error rate estimation considering dynamic voltage and frequency scaling effects
暂无分享,去创建一个
[1] B. Narasimham,et al. Characterization of Digital Single Event Transient Pulse-Widths in 130-nm and 90-nm CMOS Technologies , 2007, IEEE Transactions on Nuclear Science.
[2] Narayanan Vijaykrishnan,et al. Modeling Soft Errors at the Device and Logic Levels for Combinational Circuits , 2009, IEEE Transactions on Dependable and Secure Computing.
[3] N. Seifert,et al. Comparison of alpha-particle and neutron-induced combinational and sequential logic error rates at the 32nm technology node , 2009, 2009 IEEE International Reliability Physics Symposium.
[4] Mehdi Baradaran Tahoori,et al. Using Boolean satisfiability for computing soft error rates in early design stages , 2010, Microelectron. Reliab..
[5] B. Narasimham,et al. On-Chip Characterization of Single-Event Transient Pulsewidths , 2006, IEEE Transactions on Device and Materials Reliability.
[6] P. Hazucha,et al. Cosmic-ray soft error rate characterization of a standard 0.6-/spl mu/m CMOS process , 2000, IEEE Journal of Solid-State Circuits.
[7] H.H.K. Tang,et al. Measurement of the flux and energy spectrum of cosmic-ray induced neutrons on the ground , 2004, IEEE Transactions on Nuclear Science.
[8] Rami Melhem,et al. The effects of energy management on reliability in real-time embedded systems , 2004, ICCAD 2004.
[9] Farshad Firouzi,et al. Reliability-Aware Dynamic Voltage and Frequency Scaling , 2010, 2010 IEEE Computer Society Annual Symposium on VLSI.
[10] Narayanan Vijaykrishnan,et al. The effect of threshold voltages on the soft error rate [memory and logic circuits] , 2004, International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720).
[11] Vishwani D. Agrawal,et al. Soft Error Rates with Inertial and Logical Masking , 2009, 2009 22nd International Conference on VLSI Design.
[12] Y. Yagil,et al. A systematic approach to SER estimation and solutions , 2003, 2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual..
[13] F. Irom,et al. Frequency dependence of single-event upset in advanced commercial PowerPC microprocessors , 2004, IEEE Transactions on Nuclear Science.
[14] R. Baumann. The impact of technology scaling on soft error rate performance and limits to the efficacy of error correction , 2002, Digest. International Electron Devices Meeting,.
[15] B. M. Gordon,et al. Supply and threshold voltage scaling for low power CMOS , 1997, IEEE J. Solid State Circuits.
[16] Narayanan Vijaykrishnan,et al. SEAT-LA: a soft error analysis tool for combinational logic , 2006, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06).
[17] J. F. Ziegler,et al. Terrestrial cosmic ray intensities , 1998, IBM J. Res. Dev..
[18] David J. Lilja,et al. Guiding Circuit Level Fault-Tolerance Design with Statistical Methods , 2008, 2008 Design, Automation and Test in Europe.
[19] B. Narasimham,et al. Radiation-Induced Soft Error Rates of Advanced CMOS Bulk Devices , 2006, 2006 IEEE International Reliability Physics Symposium Proceedings.
[20] G. C. Messenger,et al. Single Event Phenomena , 1997 .
[21] D. Munteanu,et al. Modeling and Simulation of Single-Event Effects in Digital Devices and ICs , 2008, IEEE Transactions on Nuclear Science.
[22] Mehdi Baradaran Tahoori,et al. An accurate SER estimation method based on propagation probability [soft error rate] , 2005, Design, Automation and Test in Europe.
[23] P. Hazucha,et al. Impact of CMOS technology scaling on the atmospheric neutron soft error rate , 2000 .
[24] Majid Sarrafzadeh,et al. Reliability-Aware Optimization for DVS-Enabled Real-Time Embedded Systems , 2008, ISQED 2008.
[25] G. C. Messenger,et al. Collection of Charge on Junction Nodes from Ion Tracks , 1982, IEEE Transactions on Nuclear Science.
[26] R. Hokinson,et al. Historical trend in alpha-particle induced soft error rates of the Alpha/sup TM/ microprocessor , 2001, 2001 IEEE International Reliability Physics Symposium Proceedings. 39th Annual (Cat. No.00CH37167).
[27] N. Seifert,et al. Timing vulnerability factors of sequentials , 2004, IEEE Transactions on Device and Materials Reliability.
[28] Bashir M. Al-Hashimi,et al. Combined time and information redundancy for SEU-tolerance in energy-efficient real-time systems , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[29] M. Baze,et al. Comparison of error rates in combinational and sequential logic , 1997 .
[30] B. Narasimham,et al. Assessing Alpha Particle-Induced Single Event Transient Vulnerability in a 90-nm CMOS Technology , 2008, IEEE Electron Device Letters.
[31] B. Narasimham,et al. Characterization of Neutron- and Alpha-Particle-Induced Transients Leading to Soft Errors in 90-nm CMOS Technology , 2009, IEEE Transactions on Device and Materials Reliability.
[32] Krishnendu Chakrabarty,et al. Energy-Aware Fault Tolerance in Fixed-Priority Real-Time Embedded Systems , 2003, ICCAD 2003.
[33] A. R. Newton,et al. Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas , 1990 .
[34] K. J. Hass,et al. Single event transients in deep submicron CMOS , 1999, 42nd Midwest Symposium on Circuits and Systems (Cat. No.99CH36356).
[35] Margaret Martonosi,et al. Computer Architecture Techniques for Power-Efficiency , 2008, Computer Architecture Techniques for Power-Efficiency.
[36] Bashir M. Al-Hashimi,et al. Energy efficient SEU-tolerance in DVS-enabled real-time systems through information redundancy , 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..
[37] Mark Horowitz,et al. Energy-performance tradeoffs in processor architecture and circuit design: a marginal cost analysis , 2010, ISCA.
[38] James D. Meindl,et al. A physical alpha-power law MOSFET model , 1999 .
[39] Narayanan Vijaykrishnan,et al. Variation Impact on SER of Combinational Circuits , 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).
[40] N. Seifert,et al. Chip-level soft error estimation method , 2005, IEEE Transactions on Device and Materials Reliability.
[41] Fan Wang,et al. Soft Error Rate Determination For Nanometer CMOS VLSI Circuits , 2008 .
[42] Robert Baumann,et al. Soft errors in advanced computer systems , 2005, IEEE Design & Test of Computers.
[43] J. L. Leray. Effects of atmospheric neutrons on devices, at sea level and in avionics embedded systems , 2007, Microelectron. Reliab..
[44] Lorenzo Alvisi,et al. Modeling the effect of technology trends on the soft error rate of combinational logic , 2002, Proceedings International Conference on Dependable Systems and Networks.
[45] Mehdi Baradaran Tahoori,et al. Obtaining FPGA soft error rate in high performance information systems , 2009, Microelectron. Reliab..
[46] Dakai Zhu. Reliability-Aware Dynamic Energy Management in Dependable Embedded Real-Time Systems , 2006, IEEE Real Time Technology and Applications Symposium.
[47] Narayanan Vijaykrishnan,et al. Case Study of Reliability-Aware and Low-Power Design , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[48] David Blaauw,et al. An Efficient Static Algorithm for Computing the Soft Error Rates of Combinational Circuits , 2006, Proceedings of the Design Automation & Test in Europe Conference.
[49] Vishwani D. Agrawal,et al. Soft error rate determination for nanoscale sequential logic , 2010, 2010 11th International Symposium on Quality Electronic Design (ISQED).
[50] Changhong Dai,et al. Circuit-level modeling of soft errors in integrated circuits , 2005, IEEE Transactions on Device and Materials Reliability.